WTF analog design is such a royal pain in the ass!

[beer]

What the hell compels some of you people go to into analog? 😕

 

[Aharami]

exactly why I didnt take it. loved DLD (digital logic design) and DE (digital electronics)

 

[amoeba]

analog is hard but it is very secure jobwise and its easier to make your mark in analog vs digital, where everything under the sun has been exhaustively looked at.


I do digital now but I would love to switch over at some time.

 

[beer]

I can do digital systems all day.

There aren't such hardcoded inherent limits like gain/bandwidth makes analog. I can hit the gain, but then can't get the bandwidth, vice versa, and then I hit gain and bandwidth and have DC blocking capacitors the size of cinder blocks. ughhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh

 

[RaynorWolfcastle]

Originally posted by: beer
I can do digital systems all day.

There aren't such hardcoded inherent limits like gain/bandwidth makes analog. I can hit the gain, but then can't get the bandwidth, vice versa, and then I hit gain and bandwidth and have DC blocking capacitors the size of cinder blocks. ughhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh

multistage amplifiers and feedback are your friends.

<- probably going into RFICs

edit: I imagine this is school-related, post your design problem if you want and I'll take a look at it

 

[amoeba]

yes thats my point.

digital design is easier, thus more people in the field and directly competing with you.

analog is hard but once you master it, you are really at the top of your field.

 

[Analog]

Heh, I love analog.

<--------- MSEE, specialized in Analog circuit design and signal processing. Filters, amplifiers etc!

 

[beer]

Originally posted by: RaynorWolfcastle

Originally posted by: beer
I can do digital systems all day.

There aren't such hardcoded inherent limits like gain/bandwidth makes analog. I can hit the gain, but then can't get the bandwidth, vice versa, and then I hit gain and bandwidth and have DC blocking capacitors the size of cinder blocks. ughhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh

multistage amplifiers and feedback are your friends.

Of course, we had multi-stage, but that's where our high-frequency cutoff keeps on running out - since they divide in parallel we essnetially halve our high frequency cutoff each subsequent gain stage!

 

[Fritzo]

Remember...the first part of analog is anal.


I'm not sure what that means, but I'm sure it's important.

 

[RaynorWolfcastle]

Originally posted by: beer

Originally posted by: RaynorWolfcastle

Originally posted by: beer
I can do digital systems all day.

There aren't such hardcoded inherent limits like gain/bandwidth makes analog. I can hit the gain, but then can't get the bandwidth, vice versa, and then I hit gain and bandwidth and have DC blocking capacitors the size of cinder blocks. ughhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh

multistage amplifiers and feedback are your friends.

Of course, we had multi-stage, but that's where our high-frequency cutoff keeps on running out - since they divide in parallel we essnetially halve our high frequency cutoff each subsequent gain stage!

😕 What the heck are you talking about? Bandwidth is limited by the lowest frequency pole in the entire system. ie if you're using a diffamp with a 3dB freq. of 30 KHz and follow it up with an output stage with a cutoff 3 MHz then your bandwidth will be limited to 30 KHz.

So instead of just using one bulk gain stage you could split the load among two cascaded bulk gain stages so you can have better bandwidth. Ultimately, however, the real solution is to use feedback to get a slew of benefits at the expense of some gain.

 

[beer]

OK allow me to clarify.
The relevent high-frequency pole of a CE amp is basically 1/(2*pi*Rg' * Ctot), Rg' = Rb||Rg and Ctot = Cpi + Cmu (1 + gmRL' + RL'/Rg')
For our Common Collector we use on the imput stage to jack the input resistence up, you have a much more nasty equation than anything else.

And when you're trying to compute your relevent high-frequency pole, the multistage amp has one relevent high frequency pole at the parallel combination of all the individual high-frequency poles, correct?

Our low-frequency rolloff is just a matter of DC blocking capacitors that add serially

 

[RaynorWolfcastle]

well I can't too much about the theory of high frequency poles because honestly we didn't work that much with them. From the relatively simple lab experiments we performed though, it was obvious that the dominany pole was roughly that of the bulk amplification stage. I'm not sure what your design parameters are but the it looks like your dominant pole is going to be roughly where your CE amp's pole is.

Try putting a feedback resistance in the emitter of the CE amp, it'll hurt your gain a bit but it'll extend the bandwidth of that stage pretty handily. As a side note, you may be able to omit a bunch of the coupling caps if you make your circuit differential instead of single-ended.