It's not like 3 cores is naturally intrinsic to gaming consoles while being wholy unnatural in computers. Of course it's technically possible but it's probably inconvient or not efficient.
Now that I think about it, I'm sure that it's just like 16, 24, and 32-bit color (with video cards). 24-bit was possible, but it was harder to do, and just as slow as 32-bit, which is why they ended up dropping it. I'm sure we'll just be seeing some extra large dual-cores, probably with 2MB of L3 cache, which should make it worthwhile for any bargain hunter, I would think.
Originally posted by: Furen
I dont think it makes a difference what people call them as long as they get their point across.
About the die-size. The shrink from 90nm to 65nm, like the shift from 130nm to 90nm and the ones before it, should yield close to a 50% die-size reduction (not everything in a die can be shrunk so much, of course). If you follow this logic then a quad-core K8 would indeed be a ~150mm^2 part because that's around what current dual-core X2s are. That said, either AMD added a whole lot of crap to "K8L" or this wafer is an earlier run that was not die-size optimized. I'd be inclined to say that the truth lies somewhere in the middle, that this is likely an earlier run (with test logic and the like) and K8L has many more transistors than regular K8s (which is a given considering all the improvements we've been hearing about).
AMD dislikes big die sizes because it is so capacity-constrained (it, in fact, considers even 1MBx2 CPUs too big and those are 200-220mm^2). That said, I'll say that I'm kind of looking forward for the ~90mm^2 65nm X2s that should be coming out relatively soon, since they'll allow AMD to drop the prices on the X2 line even further, which will also put a bit of a fire under Intel, though on the low-end.
Calm down, my friend, I was just doing a bit of brainstorming, not claiming that I know everything absolutely or anything of the sort (all those "shoulds" and the like should show that I'm purely speculating). I said 50% simply to make the calculations easier. I'll try again. Originally posted by: Furen
Let's say AMD decided to make a quad-core K8 (not K8L). First off, you only need a single northbridge and memory controller. If you think this is small just look at the increase in die-size that AM2 brought by adding DDR2 support and (according to the inq) quad crossbar ports, I'd guess (a wild guess) that the stuff that does not need to be duplicated is around 50mm^2 of the die, which would mean that around 130mm^2 would need to be duplicated. So 2x130=260 + 50 = 310mm^2. That would be the die size for quad-core K8 on the 90nm node. Assuming a 57% die-size due to the 65nm shrink (a winchester is about 57% the die size of a newcastle) that would give us a 177mm^2 die size. I'm probably low-balling it a bit since a lot of the info needed to calculate it is purely speculation but I'm probably not off by a whole lot. Consider that a Clawhammer (at 130nm) has a die size of 193mm^2 and a Toledo (dual-core, 90nm) has a die size of 199mm^2. Same cache sizes, and Toledo added SSE3.
So that leaves a whole lot of space for the L3 cache and the K8L improvements. I'm not gonna claim that our estimates are wrong (I, too, calculated around 300mm^2 for the die size of those monsters), I'm just saying that those dice may not be final quad-core silicon.
EDIT: By the way, when I said "90mm^2 X2s" I was talking about 65nm Manchesters, lol... stupid AM2 die-sizes always screw me over (I used 150mm^2 * .6 to calculate that), so you're right about that. AMD does indeed have more production capacity but it also serves a much bigger market. AMD pretty much said that it didn't want to produce 2x1MB L2 X2s 'cause they're too big and strain its capacity, even with FAB36 and Chartered fabbing for AMD. Clawhammer was indeed huge when it came out but the process was very mature and 90nm was coming relatively soon after its introduction, and a cache-cut part came out as well after a bit. Cache was a huge chunk of Clawhammer, I dont think it's going to be that big of a part of K8L.
Originally posted by: coldpower27
Just wanted to make sure.
Heh, I doubt there is that much unneeded circuitry on the Dual Core K8, if the memory controller was boosted to serve 4 cores instead it would indeed become larger. 50mm2 of the die doesn't need to be duplicated out of 183mm2, I am not going to call you wrong, but I seriously doubt that much of the die is saved. And yes I did factor in the fact that it was a Dual Core K8 which you were talking about.
I really don't think the SSE3 instruction set is really a significant part of the die space. The San Diego core at 114mm2 already had that and Toledo was 199mm2, which is 58% the size of Toledo, so they saved 8% die space from Single to Dual Core, using that as a baseline.
I get about 190mm2 for a Quad Core K8 on the 65nm node or 316mm2 on the 90nm node. Which is mildly higher then what you have.
Well that is pretty obvious that AMD wants to optimize it's production capacity, they want to make as much money as they can, even with Fab 36 online, and the impending transistion of Fab 30 to Fab 38 and Fab 7 of Chartered Semi COnductor, as there is now rumors of the 0.5x multiplier 4000+, 4400+, 4800+ instead of having 2x1MB of cache, with the die size I predicted these cores with only 2x512KB cache now will be around the same level as Allendale. They will still prove to be more expensive in production cost then Allendale, due to the fact that AMD uses DSL SOI and that they are at least 1 layer thicker, but they are more optimal.
Soon is a matter of perspective I guess, Clawhammer came out in September 2003, and the 90nm shrink of that core didn't come till April 2005 for the desktop with San Diego, but like I said a core that intorduced a new architecture tends to be at least 200mm2 or close to it on the AMD side and this is using 200mm wafers, with 300mm wafers a ~300mm2 die size to start wouldn't be surprising. Though AMD does do a cache cut if they find they need more room to compete.
On the Intel side of the fence it varies.
Willamette on 0.18 micron is 217mm2 (Big)
Pentium M on 0.13 micron is 82.8mm2 (Small)
Core 2 Duo on 65nm is 143mm2 (Medium)
Yeah, but I would say we should stick with these die size estimates until more concrete proof comes along that can negate the picture we have seen here, 300mm2 is pretty damn realistic IMO. 65nm Quad Cores will be more expensive to produce relative to even 90nm Dual Cores, it will take hte 45nm process to bring this down to a more reasonable level.
Regarding the optical shrink I would say 60% is fair. Since the 0.13 micron to 0.09 micron shrink should yield a die size of 48% if mathematically perfect, so 58% is 10% larger, 90nm to 65nm is 52% for mathematically perfect, so 60% is fine for that.
No if Intel has 2x4MB and that is around 40% of the die for Core Architecture, then (4x512KB & 2MB) is not going to be that significant on K8L, maybe somewhere in the 30% range. But it will be enough to bring the die size to ~300mm2 or so, with the Quad Core K8L.
EDIT: Spelling, and minor additions.
).Originally posted by: Furen
Heh, the difference in real die size between Toledo and San Diego is 85mm^2. That, we can assume, is the die size of a single core with its 1MB of cache. That means that with Toledo 170mm^2 is Execution cores + L2 and 29mm^2 is the SRI, Crossbar and Memory controller and we can also say that two 512K cores take around 126mm^2 or 63mm^2 per core. I'll accept that those Barcelona cores do indeed look to be around 300mm^2 but goddam, that's freaking huge considering that AMD is so capacity constrained. Although it indeed does have 300mm wafers, FAB36 does less wafer starts per month than FAB30 so the capacity increase is not necessarily linear. AMD is also barely about to start ramping up 65nm production so the 65nm wafer starts could be way less, not to mention that dual-core Rev Gs will also take a sizeable chunk out of that.
I'll say this, If AMD's final die-size for K8L is indeed 300mm^2 then maybe AMD would be better served making 4 core Rev G parts instead of introducing such a huge die. Not as sexy but the performance deficit compared to Core would lessen a bit in quad-core parts and they would be much cheaper to produce (I'm guessing a single 200mm^2 die is cheaper to produce and package than two 150mm^2 dice in an MCP). I know that AMD claims it won't be too far behind Intel in the introduction of 45nm but producing 300mm^2 monsters for a year (more, most likely) is not all that desirable. Quad-core could indeed be limited to the extreme high end, so the volumes may be low enough, but if Intel pushes its comparatively cheap Kentsfield into the mainstream AMD will be in trouble (again
And since the next question to come up will probably "why are they round"... wafers are produced by spinning a crystal seed slowly in molten silicon, which slowly cools. As it solidifies, it solidifies into a single crystal grown on that seed. They need to be a single crystal - grain boundaries (the border between crystals) are defects. The rotation makes it a cylinder.
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