Wouldn't it seem logical for the Taulatin to work on 133fsb, 166fsb and/or 200fsb?

[MadRat]

I'm disappointed that Intel is crippling the server version of the Taulatin. They could easily have made the motherboard support AGP/PCI dividers to support the next two 33mHz increments of 166fab and 200fsb. Now we'll have to hope that VIA or some other 3rd party chipset maker takes the bold leap.

 

[Soccerman]

don't forget about clock multipliers my friend, without control over the multiplier, your FSB is limited.

 

[grant2]

Memory always runs at the same FSB speed as the processor. I believe this is to make engineering the chips & chipset easier and may improve performance (running asyncronously can cause a huge performance hit even with the faster FSB)

Therefore 133 mhz may be practical as there is 133mhz ram available, "official" 166 or 200 mhz is NOT.

On a political level, improving the taulatin would just make its trashing of higher MHZ p4's even more embarrassing. That may be why they kept celeron's at 66mhz fsb for so long... they would be just too close to their expensive p3's otherwise.

 

[BurntKooshie]

<< Memory always runs at the same FSB speed as the processor >>

I see you've never heard of via chipsets....they've been allowing asyncronous timing since Socket 7.

 

[MadRat]

It is likely VIA will institute PCI dividers past 133mHz, too. Their AGP may not get extra dividers, but with the PCI it is likely. Intel will not. There is the gist of my argument.

 

[CrackRabbit]

grant2: the clerey was originaly kept at 66mhz for so to keep it from thrashing the PII (witch it did rather handily anyways).

 

[grant2]

Burnt: you're right I don't know about any socket7 chipsets, but if i remember correctly, benchmarks with AMD cpu/ddr memory just BOMBED when the memory was run asyncronously so obviously extra engineering is required to make it run well.

Madrat: the question should by why WOULD intel put features like that in? It's only necessary for overclockers, which obviously intel has more interest in discouraging than via, and besides i doubt they're interested in increasing the performance of an &quot;old&quot; chip which crushes their p4

 

[Dulanic]

<< Burnt: you're right I don't know about any socket7 chipsets, but if i remember correctly, benchmarks with AMD cpu/ddr memory just BOMBED when the memory was run asyncronously so obviously extra engineering is required to make it run well.

Madrat: the question should by why WOULD intel put features like that in? It's only necessary for overclockers, which obviously intel has more interest in discouraging than via, and besides i doubt they're interested in increasing the performance of an &quot;old&quot; chip which crushes their p4 >>



For the ALi chipset your right, they bombed it big time when running asyncro... but the VIA chipset did a rather good job, it DID perform better running 100FSB with 133 RAM.

 

[NelsonMuntz]

Aren't a lot of people running the FSB between the Processor and the RAM different right now??? Everyone that has a 200 FSB T-bird and is running their RAM at 133 MHz is doing this. Doesn't seem to affect performance very much at all.

 

[AndyHui]

It's a little more complex for the AMD processors, since their FSB is clock doubled. They are running at 100 x 2 or 133 x 2; there is not that much of a disparity in speeds between 100 and 133.

Assuming that a 200MHz FSB processor uses 133MHz SDRAM, you could argue that the differences between the two clock speeds is too great to be cost effectively implemented. You could fix this problem by using DDR SDRAM, but seeing as Intel can't quite push DDR at the moment due to agreements with RAMBUS, I don't see this being a reality soon. Perhaps if VIA modified their Apollo Pro 266T, it might be feasible.