MadRat
Lifer
I was thinking that Intel could support DDR333 and DDR400 memory at the same time as 533fsb and 800fsb by using 133MHz as a baseline frequency. I realize that 133MHz doesn't fit into 800MHz unless its running 6x. 800MHz fits nicely if its 4x a 200fsb. It seems awfully strange, considering how many problems Intel has had in the past trying to make too big of leaps in performance, to try to engineer a 200MHz front-side bus just yet. It also seems like an uphill battle to re-engineer a true DDR400 standard to match Intel's strict design parameters since so many remarked DDR333 sticks are already out there.
Intel has a history of relaxing tolerances in order to introduce new standards. When they moved to 80286 from 8086 it allowed them to scale work while working slower internally. When they introduced the P60 its internal speed was actually slower than the 486 chips it replaced. The P2's and P3's have been released with comparable internal frequencies, true, but the P4's dropped back to a 100fsb while the P3's were operating at 133fsb. Makes me wonder if they won't pull something like this on the 800fsb they have rumor dropped at Comdex. The current P4's are running 133fsb and the next logical progression would be to move to a 166fsb, for a virtual 667MHz front-side bus.
Why would they go 6x? I'd think because the PCI and AGP standards are matched to 33/66MHz increments and a chipset based on 133MHz would be far easier to design than one based on 166MHz. No doubt they could simply pull a HDT trick and de-sync the Southbridge with the memory controller altogether, but that would add cost to the system design. If they did go to 166fsb in the immediate future they'd have a 1GHz front-side bus with the 6x multiplier. 😉
On the other hand they get 800fsb by going 100MHz x 8, too. Maybe they'll step back even more than I originally contemplated and go this route. Somehow they could make the 8x multiplier into a dual-channel 4x controller to get their 400fsb and 533fsb for backwards compatibility. This way they could later introduce a 133MHz x 8 front-side bus for 1066fsb. Whoa! My head is spinning just thinking about it.
Intel has a history of relaxing tolerances in order to introduce new standards. When they moved to 80286 from 8086 it allowed them to scale work while working slower internally. When they introduced the P60 its internal speed was actually slower than the 486 chips it replaced. The P2's and P3's have been released with comparable internal frequencies, true, but the P4's dropped back to a 100fsb while the P3's were operating at 133fsb. Makes me wonder if they won't pull something like this on the 800fsb they have rumor dropped at Comdex. The current P4's are running 133fsb and the next logical progression would be to move to a 166fsb, for a virtual 667MHz front-side bus.
Why would they go 6x? I'd think because the PCI and AGP standards are matched to 33/66MHz increments and a chipset based on 133MHz would be far easier to design than one based on 166MHz. No doubt they could simply pull a HDT trick and de-sync the Southbridge with the memory controller altogether, but that would add cost to the system design. If they did go to 166fsb in the immediate future they'd have a 1GHz front-side bus with the 6x multiplier. 😉
On the other hand they get 800fsb by going 100MHz x 8, too. Maybe they'll step back even more than I originally contemplated and go this route. Somehow they could make the 8x multiplier into a dual-channel 4x controller to get their 400fsb and 533fsb for backwards compatibility. This way they could later introduce a 133MHz x 8 front-side bus for 1066fsb. Whoa! My head is spinning just thinking about it.
