http://www.penstarsys.com/editor/AMD/64/index.html
This is a very interesting article. Read the whole thing if you can, it's just 2 pages. A lot of intriguing speculation. Here's a blurb:
So why so few T-breds? And why will it be phased out a quarter later by Barton? That brings up another subject: Barton. AMD recently changed its public roadmap and shows Barton as the desktop and mobile Athlon with 512 KB of L2 cache, as well as no longer being a SOI part. Adding 512 KB of cache is not like slapping legos together, so this project has been in motion for quite some time, and only now has AMD shown that this particular project was in the works. AMD further said that other architectural advancements will allow Barton to scale farther in clockspeed than the T-bred, even though both are made on the same process. So why is T-bred progressing so slowly? I am guessing that it has a very small development team, as other engineers are working on bigger and better things (Barton and Hammer). This lack of manpower for this project has led to the delays and the under-performance (in terms of clockspeed) of the current sampling T-bred. If the T-bred was AMD?s top priority, then it would have probably been out in greater numbers than it has by now. Using this logic, it is easy to see that T-bred is not AMD?s top priority.
For this to be true AMD had to set this project in motion around the time of the initial Palomino introduction. Oddly enough, there was an extra design team or two hanging around that needed work to do after the Palomino was released. AMD has stated that adding 64 bit functionality to the Athlon core would only add about 5% to the die, plus adding an extra 256 KB of cache to the design would still keep it under the 106 mm square size of the Hammer. If this is in fact true, how much Hammer technology would be included in Barton?
For this purpose, AMD would not have to re-invent the wheel. Much of the work on X86-64 had already been done by the time Palomino was introduced, and many of the other Hammer design advances were already researched and being run in simulation. Would it be easy enough to port these advances over to the Athlon? Or did AMD merely produce a "Hammer Lite" for use with the EV-6 bus protocol (no on-die memory controller, no HyperTransport, just the core technology please). Or perhaps it is just an Athlon XP with 512 KB of L2?
The possibility that AMD will produce X86-64 chips from top to bottom is very real, and the amount of engineering involved would be well within the realm of possibility if they were to gave the Athlon XP X86-64 functionality only. AMD has publicly stated that "architectural changes in the Athlon will allow it to further attain higher clock speeds than what is normally expected with the shrink to .13 micron." Do these changes include making the 10 stage pipeline into a 12 stage one? Will there be larger TLB?s and a more efficient Branch Predictor? Since the Hammer is based on the Athlon core, it would seem logical that much of the technology developed for the Hammer could be ported to the Athlon XP, or much of this technology could have actually been proven on the Athlon XP model. At this point, these questions are essentially meaningless without any kind of confirmation.
This is a very interesting article. Read the whole thing if you can, it's just 2 pages. A lot of intriguing speculation. Here's a blurb:
So why so few T-breds? And why will it be phased out a quarter later by Barton? That brings up another subject: Barton. AMD recently changed its public roadmap and shows Barton as the desktop and mobile Athlon with 512 KB of L2 cache, as well as no longer being a SOI part. Adding 512 KB of cache is not like slapping legos together, so this project has been in motion for quite some time, and only now has AMD shown that this particular project was in the works. AMD further said that other architectural advancements will allow Barton to scale farther in clockspeed than the T-bred, even though both are made on the same process. So why is T-bred progressing so slowly? I am guessing that it has a very small development team, as other engineers are working on bigger and better things (Barton and Hammer). This lack of manpower for this project has led to the delays and the under-performance (in terms of clockspeed) of the current sampling T-bred. If the T-bred was AMD?s top priority, then it would have probably been out in greater numbers than it has by now. Using this logic, it is easy to see that T-bred is not AMD?s top priority.
For this to be true AMD had to set this project in motion around the time of the initial Palomino introduction. Oddly enough, there was an extra design team or two hanging around that needed work to do after the Palomino was released. AMD has stated that adding 64 bit functionality to the Athlon core would only add about 5% to the die, plus adding an extra 256 KB of cache to the design would still keep it under the 106 mm square size of the Hammer. If this is in fact true, how much Hammer technology would be included in Barton?
For this purpose, AMD would not have to re-invent the wheel. Much of the work on X86-64 had already been done by the time Palomino was introduced, and many of the other Hammer design advances were already researched and being run in simulation. Would it be easy enough to port these advances over to the Athlon? Or did AMD merely produce a "Hammer Lite" for use with the EV-6 bus protocol (no on-die memory controller, no HyperTransport, just the core technology please). Or perhaps it is just an Athlon XP with 512 KB of L2?
The possibility that AMD will produce X86-64 chips from top to bottom is very real, and the amount of engineering involved would be well within the realm of possibility if they were to gave the Athlon XP X86-64 functionality only. AMD has publicly stated that "architectural changes in the Athlon will allow it to further attain higher clock speeds than what is normally expected with the shrink to .13 micron." Do these changes include making the 10 stage pipeline into a 12 stage one? Will there be larger TLB?s and a more efficient Branch Predictor? Since the Hammer is based on the Athlon core, it would seem logical that much of the technology developed for the Hammer could be ported to the Athlon XP, or much of this technology could have actually been proven on the Athlon XP model. At this point, these questions are essentially meaningless without any kind of confirmation.
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