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Will AMD be using T-RAM in Bulldozer?

Joseph F

Joseph F

Diamond Member
A long time ago I heard that AMD would be using T-RAM in their upcoming processor's cache and I was wondering if they were still going to use it. It would be awesome because of the exponentially higher density of T-RAM compared to regular SRAM. However, IIRC there is a bit of a performance trade-off so it would probably be used in L3 cache only.
 
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Dont know, but what is sure is that they used 8 transistors RAM cells
rather than usual 6Tr cell , for caches L1 and L2 , as this allow higher
speed, at the expense of reduced density in respect of the ram KB/mm2.
 
Given the known cache sizes, I would find T-ram extremely unlikely. If there were 16-64MB of L3, T-Ram would be likely. And frankly, given how much BD means to them and how risky new, untested memory technologies are, it would be borderline irresponsible to use T-ram in the first incarnation.

Now, given that GloFo has stated that T-ram will be available in 32nm, I think it's possible we will see a T-ram pipecleaner either as second-gen BD or in the BD-based fusion product, some 9-18 months from now.
 
Abwx said:
Dont know, but what is sure is that they used 8 transistors RAM cells
rather than usual 6Tr cell , for caches L1 and L2 , as this allow higher
speed, at the expense of reduced density in respect of the ram KB/mm2.
Click to expand...

Well that answers my question right there because T-RAM only uses 1 transistor per cell IIRC.
Also, as Tuna-Fish pointed out there isn't a ridiculously awesome amount of L3 cache as far as we know which would be a dead giveaway of T-RAM usage.
 
Tuna-Fish said:
Given the known cache sizes, I would find T-ram extremely unlikely. If there were 16-64MB of L3, T-Ram would be likely. And frankly, given how much BD means to them and how risky new, untested memory technologies are, it would be borderline irresponsible to use T-ram in the first incarnation.

Now, given that GloFo has stated that T-ram will be available in 32nm, I think it's possible we will see a T-ram pipecleaner either as second-gen BD or in the BD-based fusion product, some 9-18 months from now.
Click to expand...

This.

It is technically feasible, but the numbers don't stack up to support the prospect of it being implemented in Bulldozer as well as the stated truth that it would be entirely irresponsible of AMD to make Plan A be an attempt to do so many risky changes all at once.

Mind you they do need to be risky and aggressive at this time. Going copper first, and SOI, were huge advantages to AMD at the time. If TRAM was a benefit, now would be the time to roll it out.
 
Joseph F said:
Well that answers my question right there because T-RAM only uses 1 transistor per cell IIRC.
Click to expand...

Note that there is no way T-ram would be used for L1 (and it's unlikely it would be used for L2), because T-ram cannot touch the access latencies of 8T SRAM at small array sizes. As far as I know, BD L3 is still 6T.
 
Also, while everyone is talking about BD and the high-end chips, I honestly think that the fusion products will be the first with T-ram. Why? Because when you got somewhere around ~20MB of fast local storage, you can fit your framebuffer there. (assuming single display, =< full hd) This will roughly halve the off-chip bandwidth requirements of graphics, and double the amount of GPU horsepower they can sensibly put on a chip. Also, while the GPU loves bandwidth, it is not very latency-sensitive, easing the requirements they will have for the first mass-produced T-ram arrays.
 
Tuna-Fish said:
Also, while everyone is talking about BD and the high-end chips, I honestly think that the fusion products will be the first with T-ram. Why? Because when you got somewhere around ~20MB of fast local storage, you can fit your framebuffer there. (assuming single display, =< full hd) This will roughly halve the off-chip bandwidth requirements of graphics, and double the amount of GPU horsepower they can sensibly put on a chip. Also, while the GPU loves bandwidth, it is not very latency-sensitive, easing the requirements they will have for the first mass-produced T-ram arrays.
Click to expand...

Is that what IBM uses their embedded dram for? I know they use it in some common IC, just can't remember which one.
 
Idontcare said:
Is that what IBM uses their embedded dram for? I know they use it in some common IC, just can't remember which one.
Click to expand...

There is 10MB of eDRAM acting as the frame buffer in the CPU/GPU hybrid chip that is used in the xbox360. You need more in the PC world because existing games have been designed to need more. There is also 32MB of eDRAM used as the L3 cache on power7 processors. That's for a very large chip (as in it would be uneconomical for a desktop processor), but it is made on 45nm!
 
Tuna-Fish said:
There is 10MB of eDRAM acting as the frame buffer in the CPU/GPU hybrid chip that is used in the xbox360. You need more in the PC world because existing games have been designed to need more. There is also 32MB of eDRAM used as the L3 cache on power7 processors. That's for a very large chip (as in it would be uneconomical for a desktop processor), but it is made on 45nm!
Click to expand...

Check this out:
Power5.jpg

This is an IBM POWER5 CPU that has four Cores and four 36MB L3 cache dies... at 130nm! How much would a beast like this cost? I'd guess around $20-30k around the time they were popular but I don't really know much about the HPC market.
 
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Joseph F said:
:

This is an IBM POWER5 CPU that has four Cores and four 36MB L3 cache dies... at 130nm! How much would a beast like this cost? I'd guess around $20-30k around the time they were popular but I don't really know much about the HPC market.
Click to expand...

Cost is not that high since it s a multichips processor,
allowing very good yield in foundry processes.

Must be about 2/4K$ cost....
 
Tuna-Fish said:
Also, while everyone is talking about BD and the high-end chips, I honestly think that the fusion products will be the first with T-ram. Why? Because when you got somewhere around ~20MB of fast local storage, you can fit your framebuffer there. (assuming single display, =< full hd) This will roughly halve the off-chip bandwidth requirements of graphics, and double the amount of GPU horsepower they can sensibly put on a chip. Also, while the GPU loves bandwidth, it is not very latency-sensitive, easing the requirements they will have for the first mass-produced T-ram arrays.
Click to expand...


This makes sense. Could also be a response if Intel really does integrate ~ 1gb of stacked ram into Ivy Bridge.

I can't believe future CPUs (as in, next year) could possibly have more cache than my netbook 😱
 
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