Will 128-bit DDR Ram chipsets become accepted before mainstream PC1066 RDRAM use?

[MadRat]

The current buzz is to overclock the Pentium 4's on DDR-based motherboards using 145-150MHz front-side buses. The problem here is that PC2100 DDR Ram cannot cope with the bandwidth requirements of the Pentium 4 at these speeds. Asynchronous solutions also are a poor solution, too, some situations having worse memory bandwidth.

The nForce P4 chipset should eventually make its way out with that monster 128-bit pathway from the DDR memory slots. This massive bandwidth will likely feed the Pentium 4 exactly what it needs for speeds about 2GHz.

The truth is it makes less sense to go overclocked 64-bit DDR when RDRAM can handle the bandwith requirement better, even set at a 4:3 (fsb:memory) ratio. Some people are now able to coax PC800 to run at 533fsb, which is even more impressive.

So the question is, will 128-bit DDR chipsets make it before PC1066?

 

[Athlon4all]

<< The nForce P4 chipset should eventually make its way out with that monster 128-bit pathway from the DDR memory slots. This massive bandwidth will likely feed the Pentium 4 exactly what it needs for speeds about 2GHz. >>

Unfortuantely, I doubt because of nVidia-Intel relations, that a NForce P4 will ever hit the light of day unfortunately. But for the main topic......

<< So the question is, will 128-bit DDR chipsets make it before PC1066? >>

No. PC1066 will be hitting by the end of April, while the only rumored Dual Channel DDR chipset (Intel's Garnet Bay) is slated for late 2002-early 2003 release. Besides, Dual Channel DDR will be even more expensive than PC1066+850, and further, if Intel decides to change their mind, and Launch Tulloch+32-bit RIMM's, then Tullcoh+32-Bit PC1066 RIMM will be even more cheaper than DC DDR.

 

[AGodspeed]

<<

<< So the question is, will 128-bit DDR chipsets make it before PC1066? >>

No. PC1066 will be hitting by the end of April, while the only rumored Dual Channel DDR chipset (Intel's Garnet Bay) is slated for late 2002-early 2003 release. Besides, Dual Channel DDR will be even more expensive than PC1066+850, and further, if Intel decides to change their mind, and Launch Tulloch+32-bit RIMM's, then Tullcoh+32-Bit PC1066 RIMM will be even more cheaper than DC DDR. >>

Recent reports suggest that PC1066 won't be available en masse until this fall (which would mean September 1st at the earliest). I'll dig up the link for you. Even though Samsung said that PC1066 would be available (or shipping, can't remember which) during the 2Q, some different market conditions must have prompted them not to.

I'm not quite sure how much more expensive (if at all) dual channel DDR RAM chipsets are compared to RDRAM chipsets, so I'll refrain from commenting on this issue at all.

 

[Athlon4all]

<< Recent reports suggest that PC1066 won't be available en masse until this fall (which would mean September 1st at the earliest). I'll dig up the link for you. Even though Samsung said that PC1066 would be available (or shipping, can't remember which) during the 2Q, some different market conditions must have prompted them not to. >>

Hmmm. Well, that sucks if that's the case. But still though, there is RDRAM that can almost flawlessly hit PC1066 avialable (Samsung/Corsair) so for us enthusaists, it's not a huge issue that there won't be "offical" PC1066 out until fall, I mean look now with PC2700. Do we care that it's not "offical"? Not really.

<< I'm not quite sure how much more expensive (if at all) dual channel DDR RAM chipsets are compared to RDRAM chipsets, so I'll refrain from commenting on this issue at all. >>

Well, I'll just give a litte info. The reason, Dual Channel DDR chipsets (and motherboards for that matter) are so much more expensive than DC RDRAM boards is because, with RDRAM, you only need to run 2 16-bit channels from the chipset to the memory, while with DC DDR, you need to run 2 64-Bit channels which increases not only the chipset pin count tremendously, but also will make motherboards very much more expensive.

 

[AGodspeed]

<<

<< Recent reports suggest that PC1066 won't be available en masse until this fall (which would mean September 1st at the earliest). I'll dig up the link for you. Even though Samsung said that PC1066 would be available (or shipping, can't remember which) during the 2Q, some different market conditions must have prompted them not to. >>

Hmmm. Well, that sucks if that's the case. But still though, there is RDRAM that can almost flawlessly hit PC1066 avialable (Samsung/Corsair) so for us enthusaists, it's not a huge issue that there won't be "offical" PC1066 out until fall, I mean look now with PC2700. Do we care that it's not "offical"? Not really.

<< I'm not quite sure how much more expensive (if at all) dual channel DDR RAM chipsets are compared to RDRAM chipsets, so I'll refrain from commenting on this issue at all. >>

Well, I'll just give a litte info. The reason, Dual Channel DDR chipsets (and motherboards for that matter) are so much more expensive than DC RDRAM boards is because, with RDRAM, you only need to run 2 16-bit channels from the chipset to the memory, while with DC DDR, you need to run 2 64-Bit channels which increases not only the chipset pin count tremendously, but also will make motherboards very much more expensive. >>



Actually, the only reason I would doubt what you're saying is because nForce (415-D version, and even 420-D version now) aren't that expensive compared to i850 motherboards. ASUS's A7N266-C (nForce 415-D) is only 105 pounds in the UK ($150 US) and includes dual channel just like i850. i850 boards aren't that far from that price range, and i850 boards have been out more than 1 whole year whereas the A7N266-C boards just came out....

 

[Athlon4all]

<< Actually, the only reason I would doubt what you're saying is because nForce (415-D version, and even 420-D version now) aren't that expensive compared to i850 motherboards. ASUS's A7N266-C (nForce 415-D) is only $150 and includes dual channel just like i850. i850 boards aren't that far from that price range, and the A7N266-C boards just came out too.... >>

Yea, I suppose I really don't know other than nForce how expensive DC DDR is. I'm prolly off. I guess, the thing I always associated DC DDR with was extremely high pin count, so I dunno. Only time will tell I suppose.

 

[AGodspeed]

Btw, here's that link for you. Since it's GamePC talking, I wouldn't bet your life on when PC1066 will be available however....

 

[Howard]

What I'm really looking forward to is DDR-II. Anybody know its progress?

 

[AGodspeed]

<< What I'm really looking forward to is DDR-II. Anybody know its progress? >>

Supposedly it's at least another year away.

 

[Rand]

<<

I'm not quite sure how much more expensive (if at all) dual channel DDR RAM chipsets are compared to RDRAM chipsets, so I'll refrain from commenting on this issue at all. >>



Considerably more expensive and much harder to implement reliably, MANY of the past dual and quad channel DDR memory archiutectures designed in the past for the high end server market have suffered heavily from cross talk and capacitive loading on the bus which has made a stable design with multiple memory banks quite difficult to achieve. partially due to the greater number of traces from the DIMM's to the memory controller.... of course in the high end server market that disadvantage is easily off-set by the fact that Rambus is a serial architecture and hence latency inscreases severely with an increasing # of RIMMs installed which makes DRDRAM a very unattractive option for servers with large amounts of memory.

SGI/Micron collaberated on an excellent research paper a few months back about multiple channel DDR memory bus architectures... I'll see if I can find it.
One advantage to a DDR memory controller is that it can easily (Well relatively speaking as it's hardly 'easy') be implemented directly on-die the NorthBridge.... wheras DRDRAM would be much harder to implement in such a fashion.
This should ensure that DDR can potentially sustain a much lower latency operation then even faster PC1200 DRDRAM.

One comment, MadRat.... you seem to be confusing a 128bit DDR SDRAM memory controller for a dual channel 64bit DDR SDRAM memory controller. The two are not at all the same thing, and it's rather difficult to infer your meaning when you seem to be switchigh back and forth as to whether your referring to one or the other.
Contrary to nVidia's twisted terminology, the nForce is in NO WAY offers a 128bit DDR SDRAM memory controller that is quite different and in some ways quite superior to the dual channel 64bit DDR SDRAM memory bus the nForce uses.
Please remember to differentiate between the two, otherwise it's difficult to answer your question appropriately as I have little idea which you are referring to.

 

[MadRat]

Ouch, I felt a lecture rather than a correction.

 

[Daovonnaex]

128-bit PC2100 provides the exact same bandwidth as 32-bit (dual channel 16-bit) PC1066 RDRAM, is more expensive to implement, and is not necessarily as reliable. Why would you want to pair it with the Pentium 4? As for 128-bit PC2700, it provides more bandwidth than the 133MHz P4 FSB can handle, and is therefore worthless until 166FSB P4s are out, which is a long time away.

 

[Athlon4all]

Rand, thanks for the insight. I have just one question. nForce's Twinbank architechure is two seperate memory controller's that combine to provide the bandwidth requirements for both the CPU and Video Card, but also, they are linked together correct? Because Twinbank is effectively the same technology as the Cross bar Memory Controller in the >GF3, there must be load balancing involved correct? Sorry for jabbering on, my real question is what is the difference between a Dual Channel Memory controller, and the Twinbank Architchure that nForce uses? Are they just the same? If so, then what is the difference between a 128-bit DDR bus (like the one the Radeon 8500 for example uses) and a Dual Channel 64-bit DDR bus? Which is the most expensive to implement? Thanks! I'm just curious and trying to learn.

 

[Rand]

<< Ouch, I felt a lecture rather than a correction. >>




Sorry, it was meant as a correction
Your not the only one to confuse them though, so don't feel bad. Judging by your posts in the HT forum you likely understand a lot more then the majority of the people of AT.



<< nForce's Twinbank architechure is two seperate memory controller's that combine to provide the bandwidth requirements for both the CPU and Video Card, but also, they are linked together correct? >>



Well I suppose it depends on how you qualify the term 'linked', but pretty much yes they are.



<< Because Twinbank is effectively the same technology as the Cross bar Memory Controller in the >GF3, there must be load balancing involved correct? >>



So nVidia hype would lead you to believe, the reality of the matter is that the TwinBank memory controller really isnt much more then a typical dual channel memory controller, there is no extra load balancing beyond that. The TwinBank memory controller is similar to that of the GF3's crossbar memory controller in that they both have multiple memory controllers that together make up a theoretical 128bit memory controller... that's all. nVidia's PR documents... and even Anand's own nForce review make it sound as though it's something incredibly innovative and new. I think Anand fell for nVidia's hype and didnt look into the fact that it's not anything new that hasnt been done many times before in past memor controllers on other chipsets. In reality it's just a typical every day dual channel memory controller. The only thing particularly 'innovative' about it is that supports UMA for the integrated GF2 MX core, which so far as I'm aware has never been implemented in a dual channel architecture.



<< what is the difference between a Dual Channel Memory controller, and the Twinbank Architchure that nForce uses? Are they just the same? >>



The TwinBank memory architecture of the nForce is pretty much just a hyped up name for what's in reality precious little more then a traditional dual channel memory controller supporting UMA. nVidia hypes it up to seem a lot more, but in reality the differences are minimal and the end functionality is the same.



<< If so, then what is the difference between a 128-bit DDR bus (like the one the Radeon 8500 for example uses) and a Dual Channel 64-bit DDR bus? Which is the most expensive to implement >>



The Radeon8500 like the GF3 does not use a traditional 128bit DDR memory bus, in the GF3 four memory controllers are each 32-bits in width that are essentially interleaved, meaning that they all add up to the 128-bit memory controller we're used to.
The R8500 if I recall correctly has two interleaved memory controllers that are 64bits in width. The GF3 memory controller is clearly more efficient then that of the R8500, which is a large part of the reason that the GF3 tends to perform better then the R8500 despite the theoretical bandwidth disadvantage it has.
When requesting small chunks of data the 'crossbar' memory architecture is much more efficient in it's bandwidth utilization, though in large memory requests it can be a distinct disadvantage.

In a graphics card neither are significantly more expensive to implement, but the 'crossbar' architecture is much more complex which necessitates a larger die size and likely negatively impacts potential clock scalability.... though the relative efficiency gain is more then worth it.

In a memory controller in a NorthBridge chipset, a full 128bit memory bus rather then dual channel 64bit memory bus would be clearly more expensive and more difficult to design and might require a new memory standard.... I'm not certain. It wouldnt be much less inefficient and in fact for a microprocessor it may even be preferable. The biggest advantage IMHO to a true 128bit memory controller though would be that it would remove the necessity for two DIMM's to be installed to utilize both channel's like the nForce needs.
It would likely also be more stable and reliable though, as it would mostly remove all the extra interference and cross-talk inherent in a dual channel memory controller.... one wouldnt have to worry about anything like the nForce's "Super Stability mode" bug, and it would be much easier to maintain stability with multiple memory banks, it's quite viable that 8 memory banks for 4DIMM slots wouldnt be too difficult with a true 128bit memory controller whereas it's extremely difficult to manage with stability and and fast memory timings in a dual channel memory controller like the nForce.

 

[MadRat]

So, let me get this straight...

1) Radeon sends/recieves 64-bits each controller signal
2) GeFroce3 sends/recieves 32-bits each controller signal

and

1) Radeon interleaves two 64-bit pathways
2) GeForce3 interleaves four 32-bit pathways

Is this correct?

If that is the case then perhaps it would be more time efficient to first try controllers that address three interleaved 32-bit pathways rather than to go straight for one large 128-bit pathway. Three sticks of DDR RAM would probably need to be used, rather than just the pair like in the nForce. Then again, maybe 96-bit pathways would be too much trouble. If it was so easy then AMD would have probably already done 96-bit pathways for their L2 cache...

 

[Athlon4all]

Thanks Rand for the response. Lots of good stuff! I just have one comment.

I believe that the R8500 is a 128-bit DDR bus. Here's a quote from Anand's GF4 article:

<< NVIDIA's crossbar memory architecture is still present from the GeForce3. The architecture dictates that the GPU be outfitted with not one but four independent memory controllers, each with their own dedicated 32-bit DDR memory bus. All memory requests by the GPU are then split and load balanced among the individual memory controllers. What's interesting to note here is that the GeForce architecture benefits from this granularity in memory accesses while the same cannot be said for all GPU architectures. When ATI was designing the R200 core that went into the Radeon 8500 they noticed that by moving to larger 128-bit memory accesses rather than smaller memory accesses they saw a performance boost in most situations. ATI attributed this to the nature of some of their GPU caches. >>

To me, that says that it's 128-bit. But anyway. Thanks again for all the info.