Why so few clockless CPUs?

[bryanl]

AKA asynchronous CPUs, especially for low power applications?

 

[irishScott]

There are numerous examples, but in a nutshell it goes back to the reliability of the system. Asynchronous processors may work great on paper (emphasis on "may", because in many cases the added hardware logic needed to compensate for a lack of clock adds cost), but in reality are highly unstable unless employed on small-scale, specialized applications. High or lower power requirements have nothing to do with it, it's all a question of complexity and reliability.

Wikipedia sums it up nicely.
http://en.wikipedia.org/wiki/Asynchronous_circuit

In synchronous logic circuits, an electronic oscillator generates a repetitive series of equally-spaced pulses called the clock signal. The clock signal is applied to all the memory elements in the circuit, called flip-flops. The output of the flip-flops only change when triggered by the edge of the clock pulse, so changes to the logic signals throughout the circuit all begin at the same time, at regular intervals synchronized by the clock. The outputs of all the memory elements in a circuit is called the state of the circuit. The state of a synchronous circuit changes only on the clock pulse. The changes in signal require a certain amount of time to propagate through the combinational logic gates of the circuit. This is called propagation delay. The period of the clock signal is made long enough so the output of all the logic gates have time to settle to stable values before the next clock pulse. As long as this condition is met, synchronous circuits will operate stably, so they are easy to design.

However a disadvantage of synchronous circuits is that they can be slow. The maximum possible clock rate is determined by the logic path with the longest propagation delay, called the critical path. So logic paths that complete their operations quickly are idle much of the time. Another problem is that the widely distributed clock signal takes a lot of power, and must run whether the circuit is receiving inputs or not.

In asynchronous circuits, there is no clock, and the state of the circuit changes as soon as the input changes. Since they don't have to wait for a clock pulse to begin processing inputs, asynchronous circuits can be faster than synchronous circuits, and their speed is theoretically limited only by the propagation delays of the logic gates. However, asynchronous circuits are more difficult to design and subject to problems not found in synchronous circuits. This is because the resulting state of an asynchronous circuit can be sensitive to the relative arrival times of inputs at gates. If transitions on two inputs arrive at almost the same time, the circuit can go into the wrong state depending on slight differences in the propagation delays of the gates. This is called a race condition. In synchronous circuits this problem is less severe because race conditions can only occur due to inputs from outside the synchronous system, asynchronous inputs. Although some fully asynchronous digital systems have been built (see below), today asynchronous circuits are typically used in a few critical parts of otherwise synchronous systems where speed is at a premium, such as signal processing circuits.

 

[PandaBear]

I was taking a class back in school that the professor hijacked into teaching asynchronous circuits. The biggest problem is the result of calculation would not only be unstable, but the uncertainty increase exponentially as the logic complexity increase. It also is significantly larger in size as more gates are needed to keep result in stable zone between initial and final value, and the only advantage we see is the reduction of power usage due to cutting out unnecessary switching.

Not only that, a seemingly harmless small change can ripple through the entire design and force you to redo a lot of the work, and make real work unpredictable in terms of schedule and very hard to validate the result.

Since power can be reduced with other means, like low power mode or power down mode, stopping the clock, power gating, etc. Clockless circuit (let along CPU) is just not going to be a good choice.