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Discussion in 'Highly Technical' started by StrangerGuy, Mar 7, 2006.
Probably due to addressing conecerns - as the addressing is done using binary coding (which means there are X address lines coming into the memory, each can be either ON or OFF), the address range is always a power of 2.
Not really sure why exactly. Maybe it has to do with the addresses being encoded in binary and putting as many cells as you can address so that you have a fully utilized decoder in the memory. I don't think there's a technical restriction on why it HAS to be a power of two.
Tehre are several reasons why sizes go up in powers of 2. First off the memory is adressed in binary, so in order to get larger memmories you need to ad another adress bit, which allows you to double the size of the memmory. Obviously it isnt nescecarry to do so, but it just makes more sense. Also, computer geeks always want things to be in multiples of 2. Even if there was no reason at all for memmory to double it probably would. Kinda like why process sizes get half the size each generation, there is nothing saying you have to do it that way, yet it seems everyone goes from 180>130>90>65>45>32>22nm, the onyl reason is that each time it gets half as big.
RAM chips are organized in rows and columns, addressed by binary values. Making a bigger chip means adding a row or column address line - and that doubles the size of the chip.
Not always, certain computer manufacturers used to sell memory in odd sizes like 48 MB or so just to force the consumer to upgrade it from them alone
Everything in a computer is in powers of 2, since the base unit is a bit with 2 values. The Row/Column addressing posts are correct. You add one bit you double the addressing.
You can always have an "odd" total, in this case from 32- and 16-MB memory ranks. The individual RAM chip still has a capacity that is exactly a power of two.
Thats a given assumption.
In a banked memory, you'd want to use the upper bits of the address to select the bank, and the lower bits of the address to select an entry from the bank. If your bank size is not a power of two, however, this simple scheme would have problems. Consider a 48 byte bank size - you need 6 bits to address the 48 bytes, but if you have 2 banks, addresses 0110000 through 1000000 would need to somehow be mapped onto the second bank, and you can't just wire up the lower 6 address bits straight to each bank any more. This applies to actual data arrays within chips as well.