Why is Pentium 200 considered better than Pentium 200MMX?
- Thread starter 403Forbidden
- Start date
well the nice thing about them is they can be used on older motherboards, mmx requires duel voltage support. For quite a while they were comanding a nice price because of this.
Ahhhh, young paulson (though I'm hardly older...) the P200 will equal a P200mmx in 99% of programs for the simple reason that mmx instructions were virtually not at all picked up by developers. It is a ploy, kinda like the Pentium 3 makes the internet faster. 
correct me if im wrong, but a if thats a pentium pro it is faster because it has 256k on die l2 cache
EvilCoconut...you are wrong, so I will correct you.
He said P200, not Pentium Pro 200...BIG difference there!!! BTW, Pentium Pro's had 512k of off die L2 cache, not 256k on die L2 cache. Hence, it is called the Pentium 2's little brother...only difference is the core is different.
He said P200, not Pentium Pro 200...BIG difference there!!! BTW, Pentium Pro's had 512k of off die L2 cache, not 256k on die L2 cache.
Hence, it is called the Pentium 2's little brother...only difference is the core is different. 
geno
Lifer
- Dec 26, 1999
- 25,074
- 4
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Performance-wise I wouldn't classify it as better. Compatibility/Price-wise (although they're dirt cheap), I'd say that it is better than its MMX couterpart. The non-MMX is, as L vis stated, compatible with more/older mobos. There were a few MMX applications/games back when MMX was introduced, so it did have some value.
I thought that now MMX support was a given? I thought that its sorta "specialness" kinda wore off and now its just used in everything. I mean I've seen emulators and such even support it...
BoberFett is right.
A P200MMX will noticeably outperform a P200 classic in almost all applications. This is due to the added L1 cache (16k instead of 8k).
Intel was sneaky here. They had to make their MMX look like something other than a ploy for people to needlessly upgrade (which it was) so they beefed up the L1 cache on the P/MMX chips. They knew that no average consumer understands L1 cache architecture, so he would assume the MMX instructions were actually doing something.
Don't get me wrong, MMX has some uses, but it's a fairly limitted instruction set.
Modus
A P200MMX will noticeably outperform a P200 classic in almost all applications. This is due to the added L1 cache (16k instead of 8k).
Intel was sneaky here. They had to make their MMX look like something other than a ploy for people to needlessly upgrade (which it was) so they beefed up the L1 cache on the P/MMX chips. They knew that no average consumer understands L1 cache architecture, so he would assume the MMX instructions were actually doing something.
Don't get me wrong, MMX has some uses, but it's a fairly limitted instruction set.
Modus
half right... Intel has stuck with the standard harvard architecture for awhile now: a separate data and instruction L1 cache. The pentium had 8k of each (16k total - http://www.sandpile.org/impl/p54.htm). The Pmmx had 16k of each (32k total - http://www.sandpile.org/impl/p55.htm). It also had increased branch prediction, and of course, mmx, and a few other tweaks. A 166mhz P55 should be about the same performance of a P54 @ 200mhz because of the increased cache and tweaks, even more for mmx enabled things (erm...all 2 of them )
<< He said P200, not Pentium Pro 200...BIG difference there!!! BTW, Pentium Pro's had 512k of off die L2 cache, not 256k on die L2 cache. Hence, it is called the Pentium 2's little brother...only difference is the core is different. >>
. Not right. Ppro's had on package L2 cache, ranging from 256 up to 1mb of on package L2 cache.
)<< He said P200, not Pentium Pro 200...BIG difference there!!! BTW, Pentium Pro's had 512k of off die L2 cache, not 256k on die L2 cache. Hence, it is called the Pentium 2's little brother...only difference is the core is different. >>
. Not right. Ppro's had on package L2 cache, ranging from 256 up to 1mb of on package L2 cache.
yes bober is right the original p200 had 8K of L1 cache... the p200mmx had 16K...
Ppro's had anywhere from 256K to 1MB of on chip off die full speed L2(it was in an adjacent die, not in the core itself) cache and also shared the 32K L1 that the P2 had. the only real differene between the Ppro and the P2 was MMX, P2's had it Ppro didn't.... that and the fact that Ppro's were socket8 and P2's slot1
Ppro's had anywhere from 256K to 1MB of on chip off die full speed L2(it was in an adjacent die, not in the core itself) cache and also shared the 32K L1 that the P2 had. the only real differene between the Ppro and the P2 was MMX, P2's had it Ppro didn't.... that and the fact that Ppro's were socket8 and P2's slot1
i didn't even mention the L1 cache of the ppro, which is also 16 total (8k data, 8k instruction). I'm right.
MadRat
Lifer
- Oct 14, 1999
- 11,973
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A P200MMX will noticeably outperform a P200 classic in almost all applications. This is due to the added L1 cache (16k instead of 8k).
Not only that, but didn't they have twice the memory channels to the cpu core, a different FPU, and a fifth stage (as compared to four) in the instruction pipelines?
Everything you want to know about cpu's design specs: http://einstein.et.tudelft.nl/~offerman/cl.contents2.html
Tidbits:
Original Pentium prototypes at 25-33mHz! hehe
Also:
Multiprocessor support.
Upgrading: adding another Intel Pentium CPU.
Parity checking at busses.
Branch prediction (BTB: Branch Target Buffer).
8 kbyte instruction cache, 8 kbyte data cache (Harvard architecture).
Both 2-way set-associative, write-back, no write-allocate.
32 bit internal data bus (CPU - MMU (Memory Management Unit, including cache))
64 bit external data bus (MMU (Memory Management Unit, including cache) - memory).
32 bit address bus.
P24 - Early Prototype:
Technology: 0.8 micron biCMOS.
Single 32 kbyte cache: 16 kbyte code, 16 kbyte data.
P5:
Technology: 0.8 micron biCMOS.
3.1E6 transistors.
Die size: 288 mm2.
New L1 Design - 8 kbyte instruction cache, 8 kbyte data cache (Harvard architecture). Both 2-way set-associative, write-back, no write-allocate.
2-issue 5-stage superscalar with 8-stage pipelined FPU (Floating Point Unit).
P54:
Technology: 4-layer metal, 0.6 micron biCMOS.
3.1E6 transistors.
Die size: 157 mm2.
P54CT:
Technology: 4-layer metal, 0.35 micron CMOS.
3.1E6 transistors.
Die size: 90 mm2.
P54CTB - Overdrive
Technology: 4-layer metal, 0.35 micron CMOS.
4.5E6 transistors.
Die size: 141 mm2.
P55C:
Technology: 4-layer metal, 0.35 micron CMOS.
4.5E6 transistors.
Die size: 141 mm2.
Two MMX execution units; L1 16 kbyte instruction cache, 16 kbyte data cache (Harvard architecture).
P55C - Mobile
Technology: 5 layer metal, 0.25 micron CMOS.
4.5E6 transistors.
Die size: 95 mm2.
P-Pro - Early Prototype
Technology: 0.6 micron biCMOS, precharged domino logic.
5.5E6 transistors.
Die size: 306 mm2
Level 1 cache: 8 kbyte instruction, 8 kbyte data (Harvard architecture).
Multi-processor support, Superpipelined superscalar: 3-issue, 12-stage, instruction pool, fetch/decode unit, dispatch/execution unit (2 AGU (Address Generation Unit): 1 load, 1 store, 1 JEU, ECC (Error Correcting Code), Fault Analysis & Recovery ,Functional Redundancy Checking, Multi-branch prediction, data flow analysis, speculative execution, (Jump Execution Unit), 2 IEU (Integer Execution Unit), 1 FEU (Floating Execution Unit)), retire unit.
Not only that, but didn't they have twice the memory channels to the cpu core, a different FPU, and a fifth stage (as compared to four) in the instruction pipelines?
Everything you want to know about cpu's design specs: http://einstein.et.tudelft.nl/~offerman/cl.contents2.html
Tidbits:
Original Pentium prototypes at 25-33mHz! hehe
Also:
Multiprocessor support.
Upgrading: adding another Intel Pentium CPU.
Parity checking at busses.
Branch prediction (BTB: Branch Target Buffer).
8 kbyte instruction cache, 8 kbyte data cache (Harvard architecture).
Both 2-way set-associative, write-back, no write-allocate.
32 bit internal data bus (CPU - MMU (Memory Management Unit, including cache))
64 bit external data bus (MMU (Memory Management Unit, including cache) - memory).
32 bit address bus.
P24 - Early Prototype:
Technology: 0.8 micron biCMOS.
Single 32 kbyte cache: 16 kbyte code, 16 kbyte data.
P5:
Technology: 0.8 micron biCMOS.
3.1E6 transistors.
Die size: 288 mm2.
New L1 Design - 8 kbyte instruction cache, 8 kbyte data cache (Harvard architecture). Both 2-way set-associative, write-back, no write-allocate.
2-issue 5-stage superscalar with 8-stage pipelined FPU (Floating Point Unit).
P54:
Technology: 4-layer metal, 0.6 micron biCMOS.
3.1E6 transistors.
Die size: 157 mm2.
P54CT:
Technology: 4-layer metal, 0.35 micron CMOS.
3.1E6 transistors.
Die size: 90 mm2.
P54CTB - Overdrive
Technology: 4-layer metal, 0.35 micron CMOS.
4.5E6 transistors.
Die size: 141 mm2.
P55C:
Technology: 4-layer metal, 0.35 micron CMOS.
4.5E6 transistors.
Die size: 141 mm2.
Two MMX execution units; L1 16 kbyte instruction cache, 16 kbyte data cache (Harvard architecture).
P55C - Mobile
Technology: 5 layer metal, 0.25 micron CMOS.
4.5E6 transistors.
Die size: 95 mm2.
P-Pro - Early Prototype
Technology: 0.6 micron biCMOS, precharged domino logic.
5.5E6 transistors.
Die size: 306 mm2
Level 1 cache: 8 kbyte instruction, 8 kbyte data (Harvard architecture).
Multi-processor support, Superpipelined superscalar: 3-issue, 12-stage, instruction pool, fetch/decode unit, dispatch/execution unit (2 AGU (Address Generation Unit): 1 load, 1 store, 1 JEU, ECC (Error Correcting Code), Fault Analysis & Recovery ,Functional Redundancy Checking, Multi-branch prediction, data flow analysis, speculative execution, (Jump Execution Unit), 2 IEU (Integer Execution Unit), 1 FEU (Floating Execution Unit)), retire unit.
mmx itself doesn't do anything for rc5
and madrat...didn't i post that basic information?
most this stuff (not all) can be found at http://www.sandpile.org...the guy is now an ex-transmeta guy. even the branch prediction stuff
and madrat...didn't i post that basic information?
most this stuff (not all) can be found at http://www.sandpile.org...the guy is now an ex-transmeta guy. even the branch prediction stuff
MMX is great with Winamp!
RC5 too:
P166 no MMX: 230 KKey/sec
P200 w/MMX: 420 KKey/sec
I doubt the L1 cache did it...
-PJ
RC5 too:
P166 no MMX: 230 KKey/sec
P200 w/MMX: 420 KKey/sec
I doubt the L1 cache did it...
-PJ
Isnt mmx = multimedia Xtension?
Without these the cpu has to make a alot more instruction
set to equal 1 instruction set requiring for these sort of application
such as mp3 files, and anything that make uses of MMX
JPG, AVI, MPEG just to name a few would perform better with MMX
BUT anyway they are ancient cpu, I would just throw them in the trashcan as soon I get a newer cpu say K6-500
Yeap got rid of my cyrix pr166, it crashed while playing
AOEII running at normal speed using 2.9V SAD...
Without these the cpu has to make a alot more instruction
set to equal 1 instruction set requiring for these sort of application
such as mp3 files, and anything that make uses of MMX
JPG, AVI, MPEG just to name a few would perform better with MMX
BUT anyway they are ancient cpu, I would just throw them in the trashcan as soon I get a newer cpu say K6-500
Yeap got rid of my cyrix pr166, it crashed while playing
AOEII running at normal speed using 2.9V SAD...
A Pentium 200 is sometimes considered rare and "better" as older motherboards support it and within a short time of its release, 1-2 weeks, the 200MMX was released the P200 discontinued making them "rare". You see sometimes on E-gay they say "rare" 200Pentium chip.
My parents have a "rare" P200. Oh yeah, it's great! The pos Compaq it's in takes only 5 min just to start Windows 95. I do remember back in the day when those used to be fast though. Whooped the pants off my other 66mhz 486 and P133. Ahh the memories...
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