why does gate size have such an impact on speed

[omghaxcode]

hey I'm a sophomore in computer engineering and I was just kind of curious about this. this is my first time posting in highly technical so if it isn't "highly technically" just tell me to gtfo.

I have this question: it seems to me in my studies so far that complicated chips like GPUs and CPUs have a large amount of wire that take up space. It seems like the space taken up by wire would be a lot greater than the space taken up by a few transistors in a gate. Why does decreasing the gate size make such an impact on performance? I know you can get more transistors onto the chip but isn't the amount of wire a bigger issue? Does everything on GPUs and CPUs just always rely on buses to limit wire numbers? doesn't that hugely cute performance?

If I'm completely off base feel free to tell me. I would just rather embarrass myself online than in front of a professor.

 

[cprince]

I think that you're confused about gates. There are two types of gates in computer engineering. At the macro level, a gate or, more correctly, a logical gate(AND, OR, NOT, NOR, NAND, etc...) consists of many transistors put together to form a specific function. At the lower, physical electronic level, a gate is part of a MOS transistor--along with drain, source, and substrate. When they are talking about 45nm, 40nm, or 32nm process, they are talking about this physical gate size. The smaller the gate, the smaller the transistor. And the smaller the transistor, the smaller the logical gate. Thus, reducing the size of the chip and the physical distance that electrons have to travel--increasing speed.

 

[William Gaatjes]

Originally posted by: omghaxcode
hey I'm a sophomore in computer engineering and I was just kind of curious about this. this is my first time posting in highly technical so if it isn't "highly technically" just tell me to gtfo.

I have this question: it seems to me in my studies so far that complicated chips like GPUs and CPUs have a large amount of wire that take up space. It seems like the space taken up by wire would be a lot greater than the space taken up by a few transistors in a gate. Why does decreasing the gate size make such an impact on performance? I know you can get more transistors onto the chip but isn't the amount of wire a bigger issue? Does everything on GPUs and CPUs just always rely on buses to limit wire numbers? doesn't that hugely cute performance?

If I'm completely off base feel free to tell me. I would just rather embarrass myself online than in front of a professor.

If you cannot ask a question , what a strange professor.
But anyway, there is something called electrical resistance.

If you would take a garden hose and pump water through it, you get an amount of water per second. Now if you would take that same amount of water and try to pump it through a straw of the same length as the gardenhose, it would be a lot difficult to pump all that water through, especially in the same amount of time. Electrical wire has a increasing resistance with a smaller diameter if you keep using the same material and you start at the same temperature.

To stay with the water analogy, when you want a fet transistor to conduct you have to apply voltage across the gate and the source.

You can see the gate source construction as a bucket. Big process size fet's have a large bucket. When you load up that bucket with water (through gardenhose usage) it takes time to fill it up. Now if that bucket would be the size of a teacup, it would take less time to fill with the garden hose).

In essence, that is what is happening with a process shrink. You make the bucket, a cup, and from the cup again a smaller cup. Now i am also mentioning time, The smaller the bucket, the shorter time. And what is most important, you need less water. Turn water into electricity and that's it what is happening.
Now you can imagine if you would have to use the straw to fill up the bucket with water, and then the teacup it makes sense why the wiring cannot really shrink as much as the rest without using materials for better electronic conduction.

Now that bucket or teacup, is referred too in datasheets as the gate source capacitance.
There is a lot more going on then just this but this is also very important.

EDIT: typing errors... sigh...

 

[omghaxcode]

but that is why I'm saying. you can't just shrink the wire size like a gate size. my question is this: isn't the amount of wire on a chip a bigger factor than gate shrinks? lets say you have 10 gates on a chip and 25 wires. the gate size shrinks so you can fit another gate on there but you're also adding another 5 wires. why does the gate size matter so much when the amount of wire also increases with more gates.

basically is it wrong to think that the area on a chip is taken up more by wires than by gates?

 

[BrownTown]

Originally posted by: omghaxcode
but that is why I'm saying. you can't just shrink the wire size like a gate size. my question is this: isn't the amount of wire on a chip a bigger factor than gate shrinks? lets say you have 10 gates on a chip and 25 wires. the gate size shrinks so you can fit another gate on there but you're also adding another 5 wires. why does the gate size matter so much when the amount of wire also increases with more gates.

basically is it wrong to think that the area on a chip is taken up more by wires than by gates?

A chip isn't laid out in a single layer. The bottom layer is all transistors, the wires are laid out is several layers above the transistors, the smaller the transistors are the shorter the wires are which means less resistance and capacitance.

 

[omghaxcode]

oh ok that makes a lot of sense. thanks for the help.

 

[TecHNooB]

And please don't be afraid to ask questions in class -_-;

 

[Born2bwire]

It's actually a very complicated issue. There are entire research efforts devoted to finding out the optimal layouts of chips. These days, the complexity of chips is so great that you have to use computer algorithms to try and find the optimal layouts for the entire chip. One thing to note though, we don't always use real metal wires. Often the shorter interconnects between transistors are just highly doped silicon. It has some nicer properties in terms of the gate properties when we use doped silicon as opposed to metal. But it does have more problems than metal. For example, a long run will develop a voltage gradient due to resistance. So if we have a long polysilicon run that connects several gates, the voltage at the starting gate may be slightly higher than the last gate. So there are a lot of considerations to be taken into account. If you take a VLSI or solid state physics course you will get a more detailed glimpse into this sort of thing.

 

[William Gaatjes]

A chip is indeed build using multiple layers.
A modern x86 cpu is build up in a 3d fashion.

If i am not mistaken, AMD uses 10 layers stacked on top of each other for the orignal phenom architectures.
And Intel uses 7 or 8 layers stacked on to of each other for the core2 architecture.

Current architectures i really do not know.

 

[esun]

According to this:

http://download.intel.com/pres...re/News_Fact_Sheet.pdf

Intel's latest 32 nm process uses 9 copper + low-k interconnect layers.

Here's a visual example of what's happening:

http://www.silvaco.com/tech_li...97/jun/a1/a1_fig13.gif

In that image, the silicon substrate is the golden part on the bottom. The red blocks are connections between metal layers and the purple parts are the metal layers themselves.

 

[uclabachelor]

but that is why I'm saying. you can't just shrink the wire size like a gate size. my question is this: isn't the amount of wire on a chip a bigger factor than gate shrinks? lets say you have 10 gates on a chip and 25 wires. the gate size shrinks so you can fit another gate on there but you're also adding another 5 wires. why does the gate size matter so much when the amount of wire also increases with more gates.

basically is it wrong to think that the area on a chip is taken up more by wires than by gates?

A smaller fet also has less gate to source/drain capacitance, which enables the trNsistor to switch faster with less drive current.

 

[TuxDave]

It's actually a very complicated issue. There are entire research efforts devoted to finding out the optimal layouts of chips. These days, the complexity of chips is so great that you have to use computer algorithms to try and find the optimal layouts for the entire chip. One thing to note though, we don't always use real metal wires. Often the shorter interconnects between transistors are just highly doped silicon. It has some nicer properties in terms of the gate properties when we use doped silicon as opposed to metal. But it does have more problems than metal. For example, a long run will develop a voltage gradient due to resistance. So if we have a long polysilicon run that connects several gates, the voltage at the starting gate may be slightly higher than the last gate. So there are a lot of considerations to be taken into account. If you take a VLSI or solid state physics course you will get a more detailed glimpse into this sort of thing.

pffft... all you have to do is ask me and I'll draw up the best layout on the whiteboard. It's always right because I'm always right.

Edit: Except when I can't figure out where all the smilies went....

 

[exdeath]

What you are talking about is the dielectric insulated gate of the field effect transistor (FET).

Unlike a bipolar junction transistor (BJT), FETs are controlled via electric fields at an insulated gate layer (FET gate is the equal to the BJT base). Among other benefits, FETs consume much less power because there isn't a direct base-emitter current path, infinite resistance at the gate, etc.

However, you have the gate and the source-drain channel separated by a dielectric, a configuration we otherwise know as a capacitor. Capacitors have a charge and discharge time and thus have a maximum switching speed when employed as a transistor.

The smaller this capacitor, the lower the charge/discharge cycle time, and thus the faster the transistor can switch and stabilize to the new state, leading to higher clock speeds.

Also when talking about layers in chips we are talking about "metal layers" as in "9 metal layer copper process". These are just the interconnects separated by insulation material (same as multi layer printed circuit boards using vias). But it's commonly just referred to as layers, leading to the misconception that chips are "stacked" in "3D". All the transistors and active components reside only on the lowest layer infused in the silicon itself, with the exception of the dialectics and gates in the first two layers applied directly on top of the silicon before the interconnects.