You have an NMOS transistor, the gate is being driven by VDDP and the drain is connected to a cap that stores your data and the source is connected to the bit line (which is at ~VDD/2) (maybe I have the D and S backwards, either way). OK. Why do we need to drive the gate with a greater voltage than VDD? Is it because otherwise the Vgs may not be great enough to pass VDD (i.e. it would pass VDD-Vth)? My professor insinuated it had something to do with charge sharing, but maybe I heard him wrong...
Thanks!!!
Thanks!!!