Why do you used a pumped voltage to drive the word line in a RAM?

pX

Golden Member
Feb 3, 2000
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You have an NMOS transistor, the gate is being driven by VDDP and the drain is connected to a cap that stores your data and the source is connected to the bit line (which is at ~VDD/2) (maybe I have the D and S backwards, either way). OK. Why do we need to drive the gate with a greater voltage than VDD? Is it because otherwise the Vgs may not be great enough to pass VDD (i.e. it would pass VDD-Vth)? My professor insinuated it had something to do with charge sharing, but maybe I heard him wrong...
Thanks!!!
 

Mday

Lifer
Oct 14, 1999
18,647
1
81
I think it has to do with parasitic capacitance, leakages and all that. Or refreshing the cap.

I dont have a masters in CpE.
 

TuxDave

Lifer
Oct 8, 2002
10,571
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Originally posted by: pX
You have an NMOS transistor, the gate is being driven by VDDP and the drain is connected to a cap that stores your data and the source is connected to the bit line (which is at ~VDD/2) (maybe I have the D and S backwards, either way). OK. Why do we need to drive the gate with a greater voltage than VDD? Is it because otherwise the Vgs may not be great enough to pass VDD (i.e. it would pass VDD-Vth)? My professor insinuated it had something to do with charge sharing, but maybe I heard him wrong...
Thanks!!!

I agree with that. That problem will occur during low to high write operation on the DRAM.

For a read operation, the problem will occur when reading a high voltage. For low voltage DRAMs where VDD is not very large, if the capacitor is VDD, gate is VDD and the bitline is VDD/2, the transistor may not be 'on' enough for the charge from the capacitor to be shared onto the bitline. To read properly, we need a large noise margin and so we need the charge from the DRAM to be shared as much as possible to the bitline so that we can easily detect if the bitline voltage droops or rises.
 

blahblah99

Platinum Member
Oct 10, 2000
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What TuxDave Said.

If you have the capacitor charged up, it'll be at VDD/2. That means your gate voltage has to be greater than VDD/2 + Vgs, which can be a lot greater than VDD, especially if VDD low, like 1.2V for example.