Why do we still need multi*fsb formula?

[pallmall]

Memory clock is no longer tied to the cpu fsb in some advanced boards.
That is, we can set the memclock by 1mhz increments independantly to the cpu FSB.
CPU Clock calculated by multi * fsb looks like a joke to me by its inherited unnecessary restrictions.
The same logic applies to the agp, pci clock, which are now allowed to be set independantly.
Can't we just set the cpu clock directly for easy optimized tuning?
Does the cpu fsb have any roles or effects except the setting of cpu clock which is mostly restricted by its overclockability?

I know all the current cpus support only multi * fsb architecture.
But there also can be a walk-around like by calculating the sets of multi and fsb by the given cpu clocks until getting the real architecture change.
It only makes sense when the CPU FSB has no other performance effects.

If they adopt the setting of the cpu clock directly, the advantages would be :
can simplify the cpu and motherboard circuit.
can simplify the cpuclock and memory timings optimization.
easy performance analysis or comparison by providing unified fine-grained cpuclock scales.
...

I would like to get some helpful references or opinions from you.

 

[CTho9305]

When the speeds aren't nice multiples, you get larger penalties due to buffering. If you have 2 systems A and B at the same speed, they can talk on any clock edge. If they aren't the same speed, the sender has to put messages into a buffer on one of its clock edges, and the receiver won't see the message until its next edge, when it will check the buffer.

Multiplying and dividing is probably easier than setting the clocks directly, at least at high speeds.

edit: read rjain's reply for clarification.

 

[rjain]

Originally posted by: CTho9305

Multiplying and dividing is probably easier than setting the clocks directly, at least at high speeds.

To clarify what I think he's trying to say (and if he's not, I'm saying it):

Increasing and decreasing clock speeds by a simple factor is a very simple thing to do. You just need to make a circuit that oscillates 2x for each time the input circuit oscillates, for example. Therefore, all the busses in the system can be driven by the same clock generator.

However, completely independent clocks require completely independent clock generators, which get more expensive, and then you have to add buffers between the busses.

 

[pallmall]

Thanks for providing the details to ponder.

Increasing and decreasing clock speeds by a simple factor is a very simple thing to do. You just need to make a circuit that oscillates 2x for each time the input circuit oscillates, for example. Therefore, all the busses in the system can be driven by the same clock generator.

There is a way to type in the number directly, which is simpler than filling two fields.
Maybe 2x,5x or 10x can be justified by the simplicity. But how about 9.5 for a person's view?
Another way is, as I mentioned above, doing the calculation invisible, if the FSB is inavoidable.
There can be also 1x using the same clock generator with the possibility of setting the clock like 100.5.

FSB, MEMORY, AGP and PCI clocks are already independant. I don't know whether thay are using the same clock generator or not.
But it is at least saying that they are(or can be) designed to handle the bufferings without problems.
Now the problem is changing the FSB to real CPU CLOCK, if the FSB does nothing else than setting the cpu clock.

 

[rjain]

Originally posted by: pallmall
Thanks for providing the details to ponder.

Increasing and decreasing clock speeds by a simple factor is a very simple thing to do. You just need to make a circuit that oscillates 2x for each time the input circuit oscillates, for example. Therefore, all the busses in the system can be driven by the same clock generator.

There is a way to type in the number directly, which is simpler than filling two fields.
Maybe 2x,5x or 10x can be justified by the simplicity. But how about 9.5 for a person's view?
Another way is, as I mentioned above, doing the calculation invisible, if the FSB is inavoidable.
There can be also 1x using the same clock generator with the possibility of setting the clock like 100.5.

I'm talking about making the board, not the user interface. The user interface can fudge things however it wants.

FSB, MEMORY, AGP and PCI clocks are already independant. I don't know whether thay are using the same clock generator or not.

If they're totally independent, then they're probably using separate clock generators. It's not too bad because the north bridge needs to buffer lots of stuff anyway due to the different speeds and there's data going every which way, so keeping the clock lines isolated may even be a net gain in terms of the board layout.

But it is at least saying that they are(or can be) designed to handle the bufferings without problems.
Now the problem is changing the FSB to real CPU CLOCK, if the FSB does nothing else than setting the cpu clock.

Having the FSB at real cpu clock is absurd. Mobo prices would shoot through the roof because making traces that can take that frequency would be amazingly expensive. I'm not sure it really can be done without fiber optics. Then again, with hypertransport, we have a single type of bus, at a specific speed, and the "FSB" is really internal to the chip. I don't know what the real structure is there, so I can't say anything too intelligent about it.

 

[pallmall]

Originally posted by: rjainThen again, with hypertransport, we have a single type of bus, at a specific speed, and the "FSB" is really internal to the chip

Thanks, I am going to look at the new bus specification.
And yes, I am more interested in the user's view for optimization of the system.
It seems that the FSB needs to be fast enough to cover northbridge and southbridge trafics which communicate with cpu.

Considering the FSB currently unavoidable both to internal and between northbridge for optimization, the best way is to set it maximized.
It also seems to me no problem to set the multiplier like 11.111 automatically by the given cpu clock and max fsb by user.