Why do we have level 2 cache?

[jeffrey]

Any explanations why cpu manufacturers have the L1, L2, system memory, hard disk routine? Is it possible to move the L2 into a L1 and then from the expanded L1 go to memory?

This is just a question I pulled out of the air, but with the Athlon having a small path to the level2 and the p4 having a tiny level1 wouldn't this solve some issues?

I realize that the level1 is more tightly integrated into the core, but my question is it possible to have a 384k level1 and no level2? Comments are appreciated.

 

[Yzzim]

Here's a good article that explains what L2 cache is and why we have it

 

[jeffrey]

"Data is transmitted from the processor chip into main memory through the L2 cache. This stops a data bottleneck. L2 cache that's 256K in size can handle the cache functionality for up to 64Mb of DRAM. 512K of L2 cache handle caching for up to 128Mb of RAM."

This appears to be the only additional function l2 has over l1. Cpu looks in l1, if it's a miss then it hits l2, if that's a miss l2 passes the data to memory. Is is possible for l1 to tranmit data to memory and eliminate level2 in favor of a large l1.

 

[gygheyzeus]

I personally like the idea of incorporating an L3 cache on the motherboard. It would be like when you had your L2 on the cart. Instead, you've got on-die L2, and the L3 could be an option you could turn off in the BIOS. I'm talking out of my ass here.

 

[Sohcan]

The answer is simple: $$$$$

L1 caches have lower latencies than L2 caches, but they cost more. The point of a cached memory hierarchy is to balance cost vs. speed as is required by manufacturer.

 

[jeffrey]

L3 on the mobo would be a slow proposition. The farther it is away the slower it will be as a general rule. A level3 using a system bus to acces it across a 266mhz bus would pale to the level2's up to 1.33ghz speed. This is an athlon example.

 

[NaughtyusMaximus]

Basically, you want to have as much memory to have a fast route to the processor as possible. For this reason, we have L1 cache. When adding more L1 memory becomes more of a cost than its worth, slower L2 cache is used. Since L2 is still much faster and easier for the processor to access than system RAM, as much of it as possible is added to a processor (till price outweighs performance).

Thus we have Xeon's with two megs and up of L2 cache, for a large price premium, and PIII's (or Athlons, etc.) with less L2 cache for much less money.

If you recall Socket 7 days, you might remember that K6-III's were famous for their L3 cache. L1 and L2 were physically on the processor, while L3 was a 512 (and up) stick of SRAM (relativly fast compared to normal SDRAM) on the motherboard itself.

If you want to, you could look at SDRAM (or Rambus) as L4 cache in this situation. To make it simple, CPU's need RAM. The faster the better. Since SDRAM is much slower than L1 or L2 cache, it makes sense to make the line (of fast RAM) as large as possible before the CPU has to access slow SDRAM.

 

[aerialcombat]

i learned about these stuff in my Computer Architecture(CS211) class. But I don't know jack. Damn. I have an exam today in that class too!

 

[Monza]

If you would read about this thing i could recomend this book

Computer Organization by V. Carl Hamacher

isbn: 0-07-114323-8

It's quite expensive but when you need it to go to school you have to pay.

 

[BFG10K]

It's all about memory heirarchies. Generally speaking the faster the memory, the more expensive it is so you have less of it. Basically the caches are there to stop unneccesary fetches from main RAM, which is a magnitude slower than any CPU cache.

And don't forget about the register file, which is even faster than the L1 cache. It's another reason why RISC CPUs tend to be more expensive than CISC CPUs.

 

[bacillus]

<< Damn. I have an exam today in that class too! >>


hope that this doesn't come up then!
goodluck with the exam nevertheless.

 

[Compuguru]

Cause its more better than not having none