• Guest, The rules for the P & N subforum have been updated to prohibit "ad hominem" or personal attacks against other posters. See the full details in the post "Politics and News Rules & Guidelines."
  • Recovering from Halloween? Take part in our Spooky Giveaway to be in with a chance of replenishing your wardrobe. A simple riddle stands in your way. Visit the sweeptake thread over here.

why cant AMD quad pump FSB?

MDE

Lifer
Jul 17, 2003
13,197
1
81
They can do it but it would require a complete redesign of their processors and motherboards. Plus they don't really need to right now and all it does in introduce added expense. (flame away, I know it's gonna come)
 

Megatomic

Lifer
Nov 9, 2000
20,130
6
81
Perhaps it's a limitation of the Alpha EV-6 bus? Same reason why they won't officially push the FSB above 400MHz IIRC.
 

sinthon

Member
Jul 15, 2003
162
0
0
800MHZ FSB would be nice. That would definitely make AMD rock the Pentium with raw power and skill.
 

zephyrprime

Diamond Member
Feb 18, 2001
7,503
1
81
They can do it but it would require a complete redesign of their processors and motherboards. Plus they don't really need to right now and all it does in introduce added expense. (flame away, I know it's gonna come)
I think you're right on. Back when the first athlons came out quad pumping was too far out to think about. And now that opeteron has a built in mem controller, the FSB isn't so important anymore.
 

Jeff7181

Lifer
Aug 21, 2002
18,350
7
81
It's not a question of why they can't, it's a question of why they don't, which can probably be answered simply by saying, they didn't think it was necessary when they designed the chip.
 

Goi

Diamond Member
Oct 10, 1999
6,704
3
91
Originally posted by: Megatomic
Perhaps it's a limitation of the Alpha EV-6 bus? Same reason why they won't officially push the FSB above 400MHz IIRC.
 

Amorphus

Diamond Member
Mar 31, 2003
5,561
0
0
isn't the "x-pumped FSB" thing because of the separate pipelines? AMD has two longer ones, Intel has 4 shorter ones, isn't it?
 

Soulkeeper

Diamond Member
Nov 23, 2001
6,463
52
91
the eve6 protocol was never designed for reading more than on just the rising and falling edge of each clock cycle
P4 systems read four times (that's at 4 different voltages) which is very difficult to do and would require a complete redesign of not only the athlon cpu but also the chipsets
the eve6 was designed to max out at 200mhz dual pumped (400mhz) and has reached the end of it's effective lifecycle

now we can see new and interesting designs from the hammer
 

redhatlinux

Senior member
Oct 6, 2001
493
0
0
yep, its the limitation of the Alpha EV-6 bus, double pumped and maxes out at 400 mhz. When AMD chose this technology, Intel was limping along at 100 mhz. There isn't an FSB with Opteron/A64 so its now a 'non-issue'.
Hyperchannel links operating at various speeds have replaced the FSB.
 

ASK THE COMMUNITY