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Question Which CPU has most mem bandwidth per core ?

Soulkeeper

Soulkeeper

Diamond Member
Hello, I was doing some reading on zen5 and threadripper/epyc and noticed that the CCD links are the limiting factor for max mem bandwidth.
IE: 2 or 4 CCD setups can't fully saturate 8 channels of ddr5
Is the case the same on the Intel side ?
Is there any setup besides 8 or 12 CCD that can utilize many channels of ddr5 fully ? (and would require a highly threaded situation to saturate it).
I know the trend over the past 25+ years has been CPU speed greatly outpacing memory bandwidth, less bandwidth per core/thread as time goes by (and larger caches to help hide it).

I'm just interested in your thoughts on this and if anyone has been following this in detail lately.
 
The Epyc F CPUs are basically what you want for memory bandwidth bound workloads.

They have low core count per CCD and high clock frequencies.

If I recall correctly I don’t think the bottleneck for Epyc is as bad as it is for Threadripper though regarding CCDs effecting memory bandwidth. And current gen is 12 channels per socket.

If you’re getting a low core count Threadripper part it isn’t really worth going past 4 channels

The Xeons that have MRDIMM support may beat Epyc for membw, not sure.
 
If you want the highest Membandwidth available GNR with 12 Channel MRdimms is the best you can get right now.
 
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I was looking at 9965WX to pair with 8 dimms, but it seems like it only makes sense with their 8 or 12 ccd CPUs and only if using all threads. I considered Turin 9175F with it's 16 ccd, but I really don't want a server platform.
In both cases the FCLK is the limiting factor with roughly 64GB/S per core max.
This article had some very nice in depth info:
old.chipsandcheese.com

Pushing AMD’s Infinity Fabric to its Limits

I recently wrote code to test memory latency under load, seeking to reproduce data in various presentations with bandwidth on the X axis and latency on the Y axis. Ampere pretty much described how …
old.chipsandcheese.com old.chipsandcheese.com
 
Last edited:
Soulkeeper said:
I was looking at 9965WX to pair with 8 dimms, but it seems like it only makes sense with their 8 or 12 ccd CPUs and only if using all threads. I considered Turin 9175F with it's 16 ccd, but I really don't want a server platform.
In both cases the FCLK is the limiting factor with roughly 64GB/S per core max.
This article had some very nice in depth info:
old.chipsandcheese.com

Pushing AMD’s Infinity Fabric to its Limits

I recently wrote code to test memory latency under load, seeking to reproduce data in various presentations with bandwidth on the X axis and latency on the Y axis. Ampere pretty much described how …
old.chipsandcheese.com old.chipsandcheese.com
Click to expand...
Cucking client parts to one GMI link is AMD's idea of having fun.
 
Soulkeeper said:
In both cases the FCLK is the limiting factor with roughly 64GB/S per core max.
This article had some very nice in depth info:
Click to expand...
The FCLK/IF link is the choke point on Zen-based designs, so you don’t get linear scaling with added channels once you cross a certain CCD-to-memory ratio. Even on Threadripper Pro, the per-core bandwidth ceiling looks high on paper but flattens in practice.
 
Yeah, it's a shame. I guess that's just the way things are currently. Maybe something will change with zen6.
Thanks for all the conversation on this everyone.
 
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