Originally posted by: bgeh
20% for a chip that small (assuming designers have built in the usual redundancies) is frankly just ugly (TSMC's 40nm process)
20% is kinda typical though for risk-production on a qual device for a new node. Sure the top dog guys like Intel probably never start risk-production with yields that low, but for the rest of the industry this is pretty much SOP at this stage in the process maturity of a new node.
The concerns for both TSMC and their customers doesn't come from the magnitude of near time-zero yield but rather in any misses to quarterly milestones for improving yields. A miss in the yield improvement timetable is the concern as that impacts everyone's projected cost structure and earnings.
Originally posted by: Zstream
It comes down to TSMC stating they can do 40nm, unfortunately it looks like very little testing took place. Nearly impossible leakage just now shows itself. I would imagine they will need a few new set of tools or some crazy engineering/desings are needed.
Undoubtedly the leakage situation has always been there, it just didn't get tweaked and iterated on with enough learning cycles to close the gap to the spec in time for risk-production startup. I've seen this before with Iddq. With so many aspects of development happening in parallel it is not uncommon for some specs to lag others in terms of hitting their milestones, other squeakier wheels get the grease (wafers, resources) causing problems down the road as resource-starved metrics then become the squeaky problems due to knock-on effects.
So its not a case of a leakage issue just now showing itself as if it went uncharacterized and unmonitored to date, but rather this is a case of the planned/expected timely resolution of a known issue (but binnable, so it merely effects yield/cost and not reliability or qual) not happening to schedule.
In yield resolution and node ramps there are standard escalation procedures for handling these disconnects, the line will be put down temporarily while hot lots containing engineering test splits are zipped thru the fab to
more rapidly identify an acceptable solution. It is costly, which is why they don't do it unless absolutely necessary, but this is SOP for crisis management in the fab.