Who else thinks it's ridiculous that Intel uses the same bus it's been using forever only slightly upgraded? More importantly, will the later-edition Prescott or Tejas chipsets support some kind of better solution? It's doubtful they'll use Hypertransport or even Redwood, but either flavor of RapidIO or PCI-Express could be possible. Ideally they'd have a memory controller, and possibly chipset-supported memory as well. (I'd love to see an on-die parallel interface to PSiRAM; yeah right). XDR? Please?