when microsoft releases the 64bit windows......

[Matthias99]

Originally posted by: pm

Originally posted by: Matthias99
Ah, OK. I was thinking the natural thing would be to build in cache lines that were 64 bits wide, but if they're already using wider ones, they would need this kind of logic anyway. That makes sense.

I found our ISSCC paper on the implemention of the one that I worked on:
http://www.intel.com/design/itanium2/download/isscc_2002_3s.pdf
Page 18 mentions it briefly.

Using the real numbers, now the L1 pulled in 64-bit chunks and then we could mux down to 8-bits. We needed to move the bits around for endianess too. It was quite the mux circuit. I called it "The Swizzler" because we started calling all this mux and swapping "swizzling". Made people smile during presentations.

Interesting... if you didn't need to handle big/little endian, and you have 64-bit registers and a 64-bit cache, wouldn't it make more sense to load a full 64-bit value and then mask/shift it in the CPU registers? Wouldn't that simplify the cache addressing logic quite a bit?

Guess it sort of depends on the instruction set and how common these sorts of operations are... I don't really know enough about the Athlon64 to say. I've been working recently with PPC, where there are lots of 'xxx-and-shift-and-mask' type operators. Maybe in x86-64 it would make more sense to have a 'smarter' cache that can pre-mask things for you.

 

[Sunbird]

I know its off topic, but are we gonna be seeing 32bit and 64bit fanboys now too? :roll:

 

[gsellis]

Originally posted by: Sunbird
I know its off topic, but are we gonna be seeing 32bit and 64bit fanboys now too? :roll:

Yep

 

[gsellis]

Originally posted by: hugekebab
jesus, i wish id never asked the question now :s

Nah, was fine. No flame wars, so you did good