whats the point of a 4 issue core...

[miketheidiot]

I had always thought that modern 3 issue cpus had trouble filler up even their existing lines, how do they expect to take advantage of 4 and make it work?

 

[Furen]

Maybe HT will make a comeback in the future?

 

[BitByBit]

I too was surprised to learn of Intel's Next Generation architecture being a 4-issue design, given the difficulties of extracting enough ILP from x86 code to keep even two execution units busy.
It seems that Intel is going to rely heavily on compiler optimisation, in the same way that the P4 required compiler optimisation before lower-clocked P4s could outperform the P3s they were replacing.
Ontop of that, it looks as if Conroe implements very deep re-order buffers, allowing its schedulers to pick from more instructions.
We can probably expect Conroe to achieve an average IPC of perhaps between 3 and 3.5, but that is pure speculation.
It remains to be seen whether Conroe will feature Hyperthreading, but it would certainly make sense.

Edit:
Extracting ILP from 64-bit code will be easier, due to double the number of architectural registers. Perhaps this influenced Intel's decision.
Conroe will be 64-bit, afterall.