Cedar Mill a dumb shrink? It added VT! There are always tweaks whenever there's a new silicon spin. The D stepping for A64s tweaked the hell out of the memory controller but I'd still consider it a dumb shrink. Intel always adds cache whenever it does a shrink, and about SSE4... well, it could be in Conroe for all I know, since Intel also likes throwing stuff into a core and activating it until later, not to mention that its nothing earth-shattering about adding new instructions.
Prescott was a significant redesign of the architecture, not even close to a dumb shrink. Northwood was just a shrink of Willamette with additional cache, a higher frontside bus and Hyperthreading. I'm not absolutely certain about this but I believe HT was actually in Willamette, it just wasn't enabled 'till Northwood. Willamette performed horribly because it was insanely bandwidth starved, so both the cache and the FSB helped there. Northwood also introduced Intel's 130nm process and copper interconnects to the Netburst family. Remember that Conroe came out this summer, any changes we see within the next few months will only be relatively minor tweaks. I'm actually a bit skeptical about whether even Nehalem will be completely different architecture... It just seems to me like it'll be a native quad-core Conroe with a northbridge thrown into it (kind of like how the K8 was to the K7

).
Cloverton will also use a 333MHz FSB, that's nothing particularly exciting, especially considering that Yorkfield will also, supposedly, run on DDR3-1333-supporting motherboards.