No, that's not how it works ... warning, math ahead.
What is being done is map the 2^64 valid datawords into a space of 2^72 possible datawords, and spread them out in a way such that the valid datawords have the widest possible distance between each other. This distance, the so-called Hamming Distance, is a measure of how good the redundancy in your code is - the redundancy signifying the quality of error detection and performance.
Simple example with less ridiculous code spaces ... imagine a 16x16 matrix of fields. This gives you 256 fields - like on a really old 8-bit SIMM. All those positions are occupied by valid data words. Now regard your read data result as a position in this matrix. If these read data are disturbed, you'll nonetheless get a valid dataword (because your overall space does not have any invalid positions) - so you'll never know your access was off.
Now for what Parity did - double the matrix size (17x16 in our example), keep the number of valid data words, arrange them in a checkerboard pattern. Now when the disturbance in your read data is just one position, you're on an invalid field, thus you know that your read data are off. But you can't correct the mistake, since you can't see which of the nearby valid data words would have been the right one - the difference to each of them is the same. Worse, if you're off by two (or any other even number) you won't even notice because there's the next valid field already.
Fast forward to ECC. By making the matrix MUCH larger, still keeping the number of valid data words in it the same, you can arrange the few valid datawords in that large matrix such that there's much more "invalid" space around each one. So if your read data is off by a little amount, you notice that it's off, and (that's the progress) as long as you're not too far off, you can safely replace it with the nearest valid dataword to correct the error.
On ECC DIMMs, the matrix size is 256 times larger than the number of valid datawords in it, allowing for pretty neat correction capabilities - on Parity RAM, the matrix size was just twice as large, just allowing for single bit error detection.
For the real headache read this:
http://www.cs.colostate.edu/~cs530/d_info.pdf
(Hey, I had to pass an exam on this to get my CS Master

)
regards, Peter