In SSE2 enabled applications, Willy will perform well....otherwise, it 's FPU will be clock-for-clock weaker than the P3. This is because of Willy's 20-stage pipeline...it hard to appreciate how incredibly deep its pipeline is if you've never studied processor architecture. The MIPS CPUs that I've worked with have had a 5 to 7-stage pipeline (instruction fetch, instruction decode, register fetch, operand fetch, instruction execution, register store, operand store). By having such a deep pipeline, the Willy will often have pipeline holes, which occurs when a pipeline process must wait for another process to complete. This will in turn increase latency and possibly decrease the performance you can get per clock cycle.
Intel isn't too concerned about this, since they intend to have SSE2 replace the need for the FPU. There is one advantage to having such a deep pipeline: it allows Intel to ramp up the clock speeds, which is why Willy is debuting at 1.4GHz.