What will be the largest iGPU size on the laptop AMD Zen APU?

[Blitzvogel]

In 2017 for the first Zen laptop APU, with second generation HBM I am thinking AMD could probably get by with one stack of HBM (which would be either 2GB/4GB/8GB in capacity depending on the size of the dram die and how high the stack is) with 128GB/s bandwidth @ 1Gbps per pin and 256 GB/s @ 2Gbps per pin available for bandwidth.

128 GB/s is a lot of bandwidth considering I would expect a 35W laptop chip with 1024sp to be clocked pretty low.

For 1024 SPs in the 1 GHz region, I don't think 128 GB/s is enough unless there are major changes to GCN architecture like increased cache and continued progress on data and color compression like with Nvidia Maxwell. I'm also a bit skeptical on the cost of HBM coming down quickly, so it may be more conducive to use two stacks of 4 x 2 Gb instead of 4 x 4 Gb. Might as well spread the love of an 8 x 2 Gb. It also should the heat around, and if the die is produced with 2 HBM connection pads, I don't see the issue in letting the customer decide if they want something that uses just one pad or not.

Now, I'm not completely versed on HBM, are all the chips in the stack the exact same or are there slight variations in each module to supply power and data to the chips above it in the stack?

 

[ShintaiDK]

Now, I'm not completely versed on HBM, are all the chips in the stack the exact same or are there slight variations in each module to supply power and data to the chips above it in the stack?

The DRAM chips in a stack is the exact same. All sitting with a 128bit connection to the PHY. That again connects to the IMC.

A stack can constain 2, 4 or 8 chips. 8 may be cancelled again tho.

2 chips gives 512bit while both 4 and 8 gives 1024bit.

HBM2 DRAM chips will only be 8Gbit and speed between 1.6 and 2Ghz.

 

[cbn]

For 1024 SPs in the 1 GHz region, I don't think 128 GB/s is enough unless there are major changes to GCN architecture like increased cache and continued progress on data and color compression like with Nvidia Maxwell.

For a 35W laptop, 1024sp at 1000 Mhz won't happen.

And even for 95W desktop, I think the clock speeds for 1024sp will be lower than 1000 Mhz.

 

[cbn]

Remember 2Hi stacks are half bandwidth. And 2Hi HBM2 is 2GB.

Thanks for pointing that out.

I was speculating there would be a 4 Gb die for HBM1:

http://www.bit-tech.net/hardware/memory/2015/05/19/an-overview-of-high-bandwidth-memory-hbm/2

However, SK Hynix has already outlined separately what to expect from the second generation – each die will have an 8Gb capacity (whether 4Gb will be skipped or not we don't know)

4Hi HBM1 with 4 Gb dies = 2GB @ 128 GB/s if clocked at 1000 Mhz per pin.

But if that doesn't happen, AMD would have to go with a 2HI HBM2 stack for 2GB (using 8 Gb dies) with 2000 Mhz clock per pin. This yielding 128 GB/s bandwidth.

 

[ShintaiDK]

I was speculating there would be a 4 Gb die for HBM1:

http://www.bit-tech.net/hardware/memory/2015/05/19/an-overview-of-high-bandwidth-memory-hbm/2



4Hi HBM1 with 4 Gb dies = 2GB @ 128 GB/s if clocked at 1000 Mhz per pin.

But if I am wrong AMD could always make a 2HI HBM2 stack for 2GB (using 8 Gb dies) and it would still come out to 128 GB/s bandwidth with 2000 Mhz clock per pin.

HBM1 is dead end. All focus is on HBM2.

But AMDs roadmaps shows no HBM usage in the consumer space for APUs yet.

 

[cbn]

HBM1 is dead end. All focus is on HBM2.

For high end video cards, I'm sure that is the case.

But for these laptop APUs (and maybe even some lower end mobile dGPUs), I have to wonder if four slower speed 4Gb dies work out better than two 8Gb dies at twice the speed.

Both need an interposer, both need a logic chip. After that is the cost of the dies and the power consumption to consider.

What else am I missing?

 

[ShintaiDK]

For high end video cards, I'm sure that is the case.

HBM1 as a product is going away when HBM2 gets released.

 

[cbn]

HBM1 as a product is going away when HBM2 gets released.

So if HBM2 gets released in 2016, then maybe the cost structure is tolerable enough to be used in a Zen laptop APU in 2017.

If that is the case what does AMD go with? 2GB stack (2 High) or 4GB stack (4 High)?

Does the interposer and logic chip cost factor in such a way that going 4GB is only a small increase in total cost compared to 2GB? If so, maybe AMD decides to go 4GB @ 1.6 Ghz per pin for 204 GB/s bandwidth.

But with 4GB HBM2 and 204 GB/s bandwidth, how large does the iGPU have to be in order to justify such a set-up?

2048sp? Maybe?? But in a 35W or 45W laptop such an iGPU would have to be clocked very low in order to fit the power budget.

In fact, it might be that 2GB HBM2 at 128 GB/s even works for 2048sp (re: the clocks on the iGPU have to be so low for a mobile device).

With this mentioned, I feel that such a product would be extremely niche. And if it doesn't make it on mobile (where the integration helps more), I don't see such a large iGPU APU doing well on desktop. (re: dCPU + dGPU would be more cost effective and not limited by 95W power like a Desktop APU)