http://en.wikipedia.org/wiki/Athlon_64
As the memory controller is integrated onto the CPU die, there is no FSB for the system memory to base its speed upon.[52] Instead, system memory speed is obtained by using the following formula (using the ceiling function):[53]
\frac{\mathrm{CPU~speed}}{\left\lceil\frac{\mathrm{CPU~multiplier}}{\mathrm{DRAM~divider}}\right\rceil}=\mathrm{DRAM~speed}
In simpler terms, the memory is always running at a set fraction of the CPU speed, with the divisor being a whole number. An 'FSB' figure is still used to determine the CPU speed, but the RAM speed is no longer directly related to this 'FSB' figure (known otherwise as the LDT).
To summarize, the Athlon 64 architecture features two buses from the CPU. One is the HT bus to the northbridge connecting the CPU to the chipset and device attachment bus (PCIe, AGP, PCI) and the other is the memory bus which connects the on-board memory controller to the bank of either DDR or DDR2 DRAM.