Originally posted by: jaredpace
yah not too sure about how intel calculates it because, for example: An e6750 G0 stepping has a Tjmax of 80C and a Thermal Specification of 72C. That leaves only 8C for gradient at maximum temp if our E8400 theory is correct and true between wolfdale & conroe.
Oh well, Rge, what is your opinion on this one!?
Intel has stated that most cpus (probably all 65nm) have significantly raised DTS offsets to prevent throttling below tcase, per presentation at IDF, see slides 7 and 13. The chart on slide if drawn to scale could easily represent 15-20C offsets.
Intel has stated the formula for calculating temps is
diplayed temp = tj target-DTS + DTS offset
For E8400, DTS offset = 0 as measured by IR, so temp = Tj target -DTS
For E6850 or E6750 GO, DTS offset = ~20C (constant) measured by IR (Tcase is 95C on E6850 GO when DTS=0)
displayed temp = tj target (80) - DTS + 20C offset
same thing as using tj 100(effective after adding offset) - DTS
Intel clearly states this in IDF presentation, clearly showed charts with large offsets drawn, but did not give offset numbers. But they can be easily approximated with reading tcase measurements at DTS=0. Unless intel can provide offsets, that is what we are left with. But if I use 80C for my E6850 GO tjuntion than at 80C core my IHS is 95C...I would be defying the laws of physics.
What is interesting is if you use the numbers intel gave you for 65nm without offsets when you are running certain loads like linpack core temps that are displayed will approximate actual Tcase (IHS) readings but at idle you will likely see nonsensical temps displayed... ie near or below 0C.