What is the Difference between L1 and L2 Cache on a processor?

[MTP]

I know that the L2 Cache runs at full processor speed, but before it was only 1/2 or something, and that is what seperated L1 and L2, because the L1 always ran at full processor speed.

What is the difference now that the L2 Cache runs at full processor clock?

 

[DaddyG]

The main difference is how the cache is organized (L1 has seperate data and instruction sections) and latency. L1 is located closer to the execution unit and has lower latency (access time).

 

[BurntKooshie]

DaddyG - not quite true (but the right idea ). The L1 IS NOT always separated into separate caches. Most of the time, the L1 IS split up into a data cache (Dcache) and an instruction cache (Icache). Traditionally, if there was a difference in the size between the two L1 caches, it was the instruction cache being smaller (data requires FAR more room).

There is an alternative to this "split" architecture (reffered to as "harvard architecture&quot: Unified. The Cyrix 686, 686mx, M2, and Joshua version of the Cyrix III all used a single, unified L1 cache. 486's used a unified L1 cache too.

 

[DaddyG]

BurntK

Yea, I know all about unified caches. I offered a quick answer with info on current processors. I don't consider anything that Cyrix builds as current.