What is known about how Intel tests their CPU's?

[Hulk]

Does Intel test their silicon on the wafer or after the cores are cut out? Do they use a set voltage and ramp up clockspeed to a failure of some sort? Do they test at various voltages and frequencies? What type of application do they use to test silicon? How long does the test take? Do they test the max clockspeed of each core?

I would think with the number of chips they produce they must do something very quickly to allow them to accurately bin each chip. One core dead, into the dual core bin.

Alas I think this is one subject we'll never know much about.

 

[Diogenes2]

One thing we can know, is that it is highly automated..

I doubt they check for different speeds. I suspect they test all for 10%(...or so ) over the highest clock speed they sell..

 

[aigomorla]

Yes they bin.

Dr. Who from intel's Overclocking department said to me that intel does bin.

Otherwise it would make no sense for the 980X -> 990X -> 995X intel is going to try to pull later on.

So yes binning is part of intel.

 

[Spikesoldier]

everyone bins cpus.

what i have noticed is that in the past few generations, intel likes clock CPU's at about 2/3rd of what they are capable of. im as guilty as the rest of taking chips to 50% overclocks on average.

compared to intel, amd has a smaller 'safety margin', running closer to 3/4th of their maximum capable frequency for the architecture.

as a company these safety margins ensure that as the processor degrades over time and use, that they will have a good life out of them, and betting not to be inside the three years that the companies guarantee them for.

 

[Diogenes2]

Yes they bin.

Dr. Who from intel's Overclocking department said to me that intel does bin.

Otherwise it would make no sense for the 980X -> 990X -> 995X intel is going to try to pull later on.

So yes binning is part of intel.

Have you ever heard of a 980X that would not run at 995x speed - and more ?

What purpose would binning serve ?

Sounds like it would be a waste of resources.

On the other hand, wasting resources is not particularly unheard of with large companies..

 

[aigomorla]

Have you ever heard of a 980X that would not run at 995x speed - and more ?

What purpose would binning serve ?

Sounds like it would be a waste of resources.

On the other hand, wasting resources is not particularly unheard of with large companies..

im not saying it makes sense.. im just telling you what he told me when i asked him wtf intel was doing with the 980X and 990X and 995X.

And as much disbelief as one may have, the 990X do clock better then the 980X (i had both in testing), and id assume the 995X will clock a little bit better.

But there is no stepping revisions though out the linage on that cpu.

And when i asked Dr. Who why, and what intel was thinking, he said BINNING.

 

[Hulk]

One thing we can know, is that it is highly automated..

I doubt they check for different speeds. I suspect they test all for 10%(...or so ) over the highest clock speed they sell..

Seems to me that if they test all chips for 10% over max frequency or something like that then many of the chips (especially at the beginning of a process changeover) would fail. Seems like they would need a way to ramp up frequency quickly during the test to "tag" each chip at failure point.

Then they also have mobile and "S" spec chips that run at lower voltages so they must be able to test at various voltages right?

Perhaps they apply the max desktop voltages, then ramp up frequency to failure. Then they can take the fastest chips and further test at lower voltages for mobile and "S" spec parts?

There is never, ever anything said or written about this from either Intel or AMD. Seems like the most closely guarded secret and I'm not really sure why it would be?

 

[aigomorla]

There is never, ever anything said or written about this from either Intel or AMD. Seems like the most closely guarded secret and I'm not really sure why it would be?

they been binning for a long time now.

They bin the Extreme edition cpu's out from normal stock.
Also the Xeon Cpu's from normal stock.

Sad as it may seem the consumer usually gets the lower ended bin products, unless its the extreme editions.

But there is always a cherry in the pile as one can say that got missed.

But what i found out from talking to Dr. Who is the level of aggressive binning they do.

He said they sub bin inside the bin, which means, the higher model's should of been better bin'd from the lot.

Now the hard part is how do they bin? its obviously not though windows 7 and overclocking / load testing.

So whats to say there method of binning is actually the result we want in our cpus? :whiste:

 

[Dufus]

There's an article on Intels site that might give some idea of what might go on although it's primarily about thermal testing and quite old.

ftp://download.intel.com/technology/itj/q32000/pdf/thermal.pdf

Wafer sort is the first step in the test process with its main purpose being to reduce assembly costs by identifying defective die at the wafer level so that these devices are not assembled.
...
Burn-In is a batch process where up to a thousand assembled units are simultaneously stressed at elevated temperatures and voltages in order to accelerate latent reliability defects and processing problems to failure.
...
Class Test where the device undergoes a final series of tests to validate functionality and determine the speed of the part.

Or a more basic later article...

http://download.intel.com/pressroom/kits/chipmaking/Making_of_a_Chip.pdf

 

[Ben90]

While I can't add anything to what the binning specifications are, I would like to point out that a lot of chips are TDP limited. A leaky part able to exceed 2600k speeds on stock voltage may get binned as a 2400 simply due to the 95W TDP limit.

 

[Gillbot]

Have you ever heard of a 980X that would not run at 995x speed - and more ?

What purpose would binning serve ?

Sounds like it would be a waste of resources.

On the other hand, wasting resources is not particularly unheard of with large companies..

You always pick your top tier silicon for top tier parts. a 980x MAY run at 990 and 995x speeds, but may not at their INTERNAL specifications. What those specs are, we may never know though.

 

[pm]

Does Intel test their silicon on the wafer or after the cores are cut out?
Both.

Do they use a set voltage and ramp up clockspeed to a failure of some sort?
Sort of - there are various test points. A test program which sets up the voltage and ramps up either voltage or frequency or both is called a shmoo (don't ask... that's the name http://en.wikipedia.org/wiki/Shmoo_plot). They take a while to run and testers are expensive and fast testing programs are created which hit the main areas quickly without testing the intermediate points and this is a lot faster than doing shmoos.

Do they test at various voltages and frequencies?
Yes.

What type of application do they use to test silicon?
All of them and none of them. This is a complicated topic, but the tests on the testers aren't actual applications - they are snippets of applications. In the creation of the test programs, engineers figure out what the worst applications are and essentially try to write those massive programs as much shorter tests. This is harder than it sounds. Also using design knowledge - designers know what the worst conditions for their units are - you can write hand-coded assembly that often does better than real applications at testing a unit's function. So the testers don't run real applications - they are running abstractions of real applications.

How long does the test take?
Less than 1 second usually.

Do they test the max clockspeed of each core?
Yes.

For an overview, the first step after fabrication is called sort. It's a wafer test that tests the full wafer. It's done at speed to some extent but power-delivery is an issue so it's not a full power test. Checks are done on the cache, and as many transistors as possible are tested to make sure that they can toggle on/off. Then the parts are packaged and they go to "class" testing which is done at multiple temperatures and voltages and they are binned and fused. Then they go to burn-in testing which is an accelerated stress test environment designed to weed out early failures. Then back to class for post burn-in binning and then they are shipped.

There's a pretty graphical overview of this here:
http://download.intel.com/pressroom/kits/chipmaking/Making_of_a_Chip.pdf (Adobe PDF)

See pages 10, 11 and 12. They skip burn-in but otherwise it's a good high level overview... with cool pictures.

Patrick Mahoney
Senior Design Engineer
Intel Corp.

* not a spokesperson for Intel Corp. *

 

[exar333]

Does Intel test their silicon on the wafer or after the cores are cut out?
Both.

Do they use a set voltage and ramp up clockspeed to a failure of some sort?
Sort of - there are various test points. A test program which sets up the voltage and ramps up either voltage or frequency or both is called a shmoo (don't ask... that's the name http://en.wikipedia.org/wiki/Shmoo_plot). They take a while to run and testers are expensive and fast testing programs are created which hit the main areas quickly without testing the intermediate points and this is a lot faster than doing shmoos.

Do they test at various voltages and frequencies?
Yes.

What type of application do they use to test silicon?
All of them and none of them. This is a complicated topic, but the tests on the testers aren't actual applications - they are snippets of applications. In the creation of the test programs, engineers figure out what the worst applications are and essentially try to write those massive programs as much shorter tests. This is harder than it sounds. Also using design knowledge - designers know what the worst conditions for their units are - you can write hand-coded assembly that often does better than real applications at testing a unit's function. So the testers don't run real applications - they are running abstractions of real applications.

How long does the test take?
Less than 1 second usually.

Do they test the max clockspeed of each core?
Yes.

For an overview, the first step after fabrication is called sort. It's a wafer test that tests the full wafer. It's done at speed to some extent but power-delivery is an issue so it's not a full power test. Checks are done on the cache, and as many transistors as possible are tested to make sure that they can toggle on/off. Then the parts are packaged and they go to "class" testing which is done at multiple temperatures and voltages and they are binned and fused. Then they go to burn-in testing which is an accelerated stress test environment designed to weed out early failures. Then back to class for post burn-in binning and then they are shipped.

There's a pretty graphical overview of this here:
http://download.intel.com/pressroom/kits/chipmaking/Making_of_a_Chip.pdf (Adobe PDF)

See pages 10, 11 and 12. They skip burn-in but otherwise it's a good high level overview... with cool pictures.

Patrick Mahoney
Senior Design Engineer
Intel Corp.

* not a spokesperson for Intel Corp. *

Awesome information pm, thanks!

 

[bryanW1995]

Awesome information pm, thanks!

yes, quite an interesting read. well worth the time.

 

[Hulk]

Nice! Thanks.

 

[Rifter]

How long does the test take?
Less than 1 second usually.

Can i send you my next CPU to test? it usualy takes me weeks after i overclock before im convinced its stable, 1 second would be SWEET

 

[fire400]

custom made motherboards.

custom software application.

test linux and red hat extensively for server market/security/gov./etc.

they test all the games available in the public market.

liquid nitrogen controlled environments, cooling tests.

they also have custom cpu samples that will never be released to 3rd party publicists/reviewers.

to share a few things.

if you're a die hard fan, take computer engineering/science and try out for their s-i-g companies, or for intel themselves.

 

[veri745]

Does Intel test their silicon on the wafer or after the cores are cut out?
Both.

Do they use a set voltage and ramp up clockspeed to a failure of some sort?
Sort of - there are various test points. A test program which sets up the voltage and ramps up either voltage or frequency or both is called a shmoo (don't ask... that's the name http://en.wikipedia.org/wiki/Shmoo_plot). They take a while to run and testers are expensive and fast testing programs are created which hit the main areas quickly without testing the intermediate points and this is a lot faster than doing shmoos.

Do they test at various voltages and frequencies?
Yes.

What type of application do they use to test silicon?
All of them and none of them. This is a complicated topic, but the tests on the testers aren't actual applications - they are snippets of applications. In the creation of the test programs, engineers figure out what the worst applications are and essentially try to write those massive programs as much shorter tests. This is harder than it sounds. Also using design knowledge - designers know what the worst conditions for their units are - you can write hand-coded assembly that often does better than real applications at testing a unit's function. So the testers don't run real applications - they are running abstractions of real applications.

How long does the test take?
Less than 1 second usually.

Do they test the max clockspeed of each core?
Yes.

For an overview, the first step after fabrication is called sort. It's a wafer test that tests the full wafer. It's done at speed to some extent but power-delivery is an issue so it's not a full power test. Checks are done on the cache, and as many transistors as possible are tested to make sure that they can toggle on/off. Then the parts are packaged and they go to "class" testing which is done at multiple temperatures and voltages and they are binned and fused. Then they go to burn-in testing which is an accelerated stress test environment designed to weed out early failures. Then back to class for post burn-in binning and then they are shipped.

There's a pretty graphical overview of this here:
http://download.intel.com/pressroom/kits/chipmaking/Making_of_a_Chip.pdf (Adobe PDF)

See pages 10, 11 and 12. They skip burn-in but otherwise it's a good high level overview... with cool pictures.

Patrick Mahoney
Senior Design Engineer
Intel Corp.

* not a spokesperson for Intel Corp. *

Does Intel do any testing at the system level? For production or only characterization?

 

[pm]

I'm glad people found the post helpful.

Does Intel do any testing at the system level? For production or only characterization?

For characterization, yes. There's always lots of system characterization. "Characterization" if you don't speak engineer, is testing to find out the operating window of the part - in other words, max and min voltages, frequencies, power, and thermal.

For production, there's a sampling for quality control, but otherwise, no, not in normal circumstances for volume products. The term "production system testing" is a bit more readable, but it means "does Intel stick every part that comes out into a system for testing before it's shipped".

 

[dmens]

^

Correct me if I'm wrong (since I worked solely at the tester end) but system level testing actually generates a lot of the worst case test patterns. I guess characterization naturally needs to test generation.

One goal is to minimize the discrepancy between in-depth system testing and what the 1-second production tests can affirm, which as pm said is not as easy as it sounds.

 

[pm]

^

Correct me if I'm wrong (since I worked solely at the tester end) but system level testing actually generates a lot of the worst case test patterns. I guess characterization naturally needs to test generation.

Yeah, you guys in JF do things slightly differently compared to here in FC. But yeah, you are right. I forgot about that - I'm too used to the method we use.

 

[Dufus]

Yeah, you guys in JF do things slightly differently compared to here in FC.

They don't use the same test criteria at all plants.

 

[pm]

They don't use the same test criteria at all plants.

It's not the method used for testing, it's the method used to get tests for the testers.

So say you have a program - like Prime95 or something like that - and you decide this is a great program for testing a particular circuit in the floating point unit because when you run it, it find a bunch of processors that the tester said should run at 3GHz, failed at 2.8GHz running this great program. So now you have this program that's compiled to run under Windows and requires you to boot an operating system to run it, and you need to get it to run in under well under 1 second on a tester...? (because you have to get all of the tests to run in under a second on a tester).

As I said above, at first glance it might seem like an easy enough problem - you get the C code or something and disassemble it, take the core assembly and run that... but that is very engineer-time intensive, and you need to do this for a LOT of tests. You can't afford to have an engineer spend a week trying to get one test this way, you need to get a lot of them quickly. And what if the problem isn't really the core algorithm in your application - Prime95 in this example - but in the interaction of Prime95 with the OS for some reason. Or, more realistically, say that it only happens when you run Linpack and Prime95 at the same time... now when you start to think about how to port that, you can start to see that it's a suprisingly complex problem.

So, there are other methods. I'm not sure that I can go into too much detail - I think it's safe to say that Intel Legal wouldn't be pleased if I started discussing it on Anandtech. But the root of it is that there's a traditional way - which is used in Jones Farm (JF) and a lot of the rest of Intel - and then there's a new way that we've been doing in Fort Collins (FC). I'm not sure that the company has come to a consensus about which way is better yet... although since I helped develop the FC method, I have my rather obvious opinion.

 

[dmens]

I have my rather obvious opinion.

Maybe you ought to spread the gospel because I despise the system -> tester content porting. I lost about a year of my life on that for nehalem.

Also I'm in RA now. Joined what used to be a graphics card group.

Even less DFX capability, hurray.

 

[Dufus]

Ahh, I see. My misunderstanding, thanks for clearing it up.

How would the errata fit in with this?