What is an EV6 protocol used by athlons

[thermalpaste]

I heard that the chipsets for the AMD athlon CPU uses an EV6 protocol. How different is this from Intel's GTL+ protocol? How does it exactly work?

 

[borealiss]

GTL+ is not a point-to-point protocol. EV6, like hypertransport, is.

 

[borealiss]

Protocol specifics remains proprietary I believe. I'l have to check with a coworker. If you want a good definition of how a modern point-to-point protocol works, the hypertransport specs are good start, and the standard is open and available for download. If you're more interested in point-to-point topology among peripheral devices, check out PCI Express. I can't comment on much about PCI Express, most of my knowledge lies in HT. Usually in P2P protocols, you will have more than 1 bus available to the system, or the device will be able to split the bus into different "lanes" to direct traffic between devices. I believe PCI Express can do the lane-splitting, I may be wrong. Depending on how I/O is directed, (strobes, packets, etc...), usually there's an associated I/O address per transaction to specify from target to destination. The data gets routed usually by a set of map registers that are in a device that's on the bus. That way it'll know if it owns the data or if it needs to forward it on one of its corresponding buses that it controls. PCI, to an extent,works something like this. If you have an I/O address for a cycle that doesn't map to any devices on the PCI bus the arbiter usually will forward it to the ISA/LPC bus where your super I/O controller and other slow devices lie. PCI, however, is not a P2P protocol, this is just an example of how I/O would get forwarded to a target. P2P buses are similar, but in most cases you can have traffic going both ways (full duplex) on a P2P bus. Hope that explains some of it.

 

[thermalpaste]

Originally posted by: borealiss
Protocol specifics remains proprietary I believe. I'l have to check with a coworker. If you want a good definition of how a modern point-to-point protocol works, the hypertransport specs are good start, and the standard is open and available for download. If you're more interested in point-to-point topology among peripheral devices, check out PCI Express. I can't comment on much about PCI Express, most of my knowledge lies in HT. Usually in P2P protocols, you will have more than 1 bus available to the system, or the device will be able to split the bus into different "lanes" to direct traffic between devices. I believe PCI Express can do the lane-splitting, I may be wrong. Depending on how I/O is directed, (strobes, packets, etc...), usually there's an associated I/O address per transaction to specify from target to destination. The data gets routed usually by a set of map registers that are in a device that's on the bus. That way it'll know if it owns the data or if it needs to forward it on one of its corresponding buses that it controls. PCI, to an extent,works something like this. If you have an I/O address for a cycle that doesn't map to any devices on the PCI bus the arbiter usually will forward it to the ISA/LPC bus where your super I/O controller and other slow devices lie. PCI, however, is not a P2P protocol, this is just an example of how I/O would get forwarded to a target. P2P buses are similar, but in most cases you can have traffic going both ways (full duplex) on a P2P bus. Hope that explains some of it.

(Y)