What is a PLL?

[Creedyou]

I downloaded a CPU monitor program, CPUCool, and I came across a setting I am not familiar with. It asked for my PLL manufacturer and type. What is a PLL? This setting was in the "motherboard FSB/CPU speed" section.

 

[Demon-Xanth]

"Phase Locked Loop"

Basically it's a way of keeping a voltage steady by using a Voltage Controlled Oscillator (VCO) and when the oscillations start to drift, the circuitry pulls it back in making sure the signal and a reference signal are always in phase.

I know it's not the best description, but hopefully it'll give you an idea.

 

[CTho9305]

I thought it was used to generate a steady clock pulse.

 

[pm]

No offense, Demon, but your description of "keeping a voltage steady" makes it sound like a power supply. 🙂

It's a way of synchronizing one digital oscillating signal to another using the method described in Demon's post.

There's a thorough description here.

In a computer system everything is synchronized to a core clock that is generated using a crystal (piezoelectric typically using quartz) based clock signal and all other clock signals are derived from this signal. Look at your motherboard and somewhere on there will be a small (3m x 7mm or so) silver box that has something like "14.318" on it (typically) which is 14.318MHz. This generates the primary clock signal for the entire system and all other clocks are derived in respect to this one. In order to synchronize the clocks so that the rise edge of one is lined up with another, a PLL is used to keep the phases of the clock signals synchronized. A PLL is used on the CPU (typically, in the "old" days of the late 80's and early 90's the PLL was typically off-chip and the clock was driven on to the core from an external source). to synchronize the bus clock with the core clock and any clocks that may exist on the chip.

 

[Demon-Xanth]

Sorry, I had to head off to a meeting :/

 

[rbhawcroft]

The problem with digital signals is that they are 'inteligent' but are worked on by 'dumb' hardware. So the problem is that if you have a data signal coming in in the logic/ digital format of 1's and o's represented by voltage = say >.6 and voltage say = < .4 of maximum voltage level, 5V in PC's, then the chip has to recognise the rate the data is coming in at and roughly when it is coming in. PPL is an oscilator in the receiving chip that in inline/ synchronised in phase, and data rate with the incoming signal. If the chip didnt know what to expect then it would have to buffer data while it got a big enough sample to figure out the data rate and there fore whether a signal is 111 or 1111, or 10 or 1100, or 110011 or 111000111, you see? Its a crap explanation sorry.

 

[CTho9305]

to answer the non-technical part of your question, what PLL you have, find the crystal pm described. there may be more than one. somewhere near it should be a rectangular chip about as wide as hte crystal is long, and about 2x as long as it is wide. It usually says "ICS" or "winbond" on it. then read the numbers off 🙂

 

[pm]

There's the cystal and there's the motherboard clock generator that uses PLL's to generate all of the main non-CPU clocks in the system. The clock generator is usually a long rectangular IC chip. It's usually close to the CPU (so once you get past the AGP slot and start moving "down" along the PCI's you have probably gone too far) and it usually has ICS on it like CTho mentioned.

 

[Demon-Xanth]

An easy way to identify which IC is the PLL is that they are typically surrouned closely by small resistors and capacitors.