What exactly is Frontside Bus?

[Deelow]

Is it the connection between CPU and RAM, CPU and chipset? I guess I'm a little confused because the P4 has a quad-pumped 100Mhz FSB and AMD uses a 200Mhz FSB and if it were the connection between CPU and RAM, you'd have to use 200Mhz ram with an Athlon, right? Please help me, as you can see I'm a bit confused.

Thank you.

 

[DaddyG]

The FSB connects the CPU and the Northbridge of the chipset. On most modern chipsets the memory bus is run asynchronously from the FSB. The memory bus runs from the Northbridge to the memory. VIA chipsets allow the memory bus to be run at the FSB (100 in the case of the Athlon since the memory is not doing the dubble pump dance) plus OR minus the PCI bus. The reult being memory at 66, 100 or 133. Hope this helps.

 

[toph99]

the Front Side Bus(FSB) is what the system as a whole runs on. let's say that you have a 100mhz FSB and a Pentium III 500mhz. the PCI slots will run on a 33mhz bus(a divider of 1/3 i believe, but this is just a guess) and the ram will run at 100mhz, and the CPU will run at 100mhz X 5 = 500mhz
now for the P4 and Athlons, with their DDR(Double Data Rate) FSB(100mhz X 2 = 200mhz) it is only, AFAIK, the interface between the CPU and the North Bridge(chipset) the ram can run at either 100mhz or 133mhz(depending on the kind of ram) and the PCI still runs at 33mhz

hope i didn't confuse you too much and if i made any mistakes(long day) i'm sure someone will correct me

<edit> i see someone beat me to it </edit>

 

[Moonbender]

Mostly the FSB means the connection between chipset and CPU. There is no AMD CPU running at a 200 Mhz FSB. All AMDs up to now run at a 100 Mhz bus, some very recent models run at 133 Mhz. However, the connection between the CPU and the chipset features DDR - double data rate.
So effectively the Thunderbirds and Durons are running at a bus of 200 or 266 Mhz.
As I understand it, the quad-pumped P4 is basically the same, only instead of doubling the data rate, it is quadrupled (effectively making it a 400 Mhz FSB).

The RAM connection speed is closely related to the FSB. The only exception to that rule is the VIA KT133 chipset which happens so be the chipset of nearly all Socket A mobos. You can set the clock of the RAM to be higher than the FSB (the RAM is run asynchronous), which makes running PC133 at full speed on a 100 Mhz system possible.
But asynchronous RAM, as neat as it is, is quite difficult to implement for the chipset developers (or so I read), so the KT133 might very well be one of the few chipsets we see with that feature.
Usually it is FSB = RAM clock.

Another thing which adds to the confusion is the upcoming DDR RAM (which has nothing really to do with the DDR bus of AMD CPUs). Once again, the RAM runs at either 100 or 133 Mhz, but transports twice as much data, so effectively it's running at 200 or 266 Mhz.

 

[Deelow]

Thanks a lot for the replies!

Ok, so does all data coming from the PCI bus, memory bus, etc. all come to the Northbridge at their respective speeds (PCI=33, memory=100/133) and then get shot from the Northbridge to the CPU at 400Mhz (P4) or 200Mhz (Athlon)? Is that how this works?

Thanks again.

PS--I actually understand how DDR transfers work...rising/falling edges of the clock, etc.

 

[Moonbender]

Actually I don't know exactly, but what you guess sounds reasonable enough.

 

[toph99]

the PCI/ISA actually goes to the Southbridge(smaller chip near the slots) and then to the Northbridge, but yeah, you got the idea

 

[Deelow]

Ok, thanks a ton for your help guys! I really appreciate it.

Have a great day.

 

[DaddyG]

Moonbender,

You made the mistake of mixing the clock with the bus.

AMD does use a 200mhz FSB, the bus is CLOCKED by a 100mhz clock but since the data on the bus is valid at the leading AND trailing edges of the clock, the BUS IS ACTUALLY 200 mhz. If you look at data on a bus using a DDR clock or a clock at twice the rate, using only the leading edge of the clock, they will appear the same.

To answer Deelow question, yep, your'e right, the Northbridge acts as a big Data Gatherer. Communicating with the Southbridge via the PCI bus. The South does all the grunt work with the I/O devices, except AGP, and the North handles the data movement to the CPU.