What exactly does "0.13 micron process" mean? and how does it help?

[Quad]

i'm just a little confused

i know that the length of the copper interconnects are 0.13 micron. i also know that the smaller the interconnects, the less power is required, thus a lower amount of heat is given off. but:

1) What exactly are interconnects? do they connect transistors together? or connect different layers on the cpu? or ____
2) How do smaller interconnects result in higher clocks speeds and higher performance?

thx in advance

 

[SexyK]

Actually, all the transistors on the chip average out to .13u. Some are as small as .09 (i believe) and some are a bit larger. The actual interconnects are channels that connect different layers of tansistors, so they aren't usually refered to by their feature size. .13u refers to the transistors themselves. Anyway, i think that smaller transistors are faster based on lowered resitance to current, and obviously the lower heat output. A cool chip is a fast chip. There are probably other reasons for the speed increase also. Maybe someone else can get into more detail of the physics involved.

Kramer

 

[Lithium381]

<< . A cool chip is a fast chip. >>



And a cool chip is also a happy chip Fast is good too

 

[Nate420]

I believe the shorter distance the electrical signals have to travel also effects the overall speed(seems trivial though, considering electricity travels at the speed of light..I think), and the smaller the process, the more transistors they can pack into a chip.

 

[Quad]

but isn't the clock speed of a cpu the rate at which the transistors flick on and off? if this is the case...then all 0.13 micron does is pack more transistors into the chip...allowing for more work to be done per clock cycle, thus boosting performance. that i can see. but how does 0.13 micron allow for higher clock speeds?

thx in advance

 

[imgod2u]

Ok, usually, the jump to .13 micron only means that the transister size is getting smaller (in the case of the Northwood, the extra space saved was used for 512KB more cache). The increase in speed of electric flow (due to the decrease size of interconnects) is pretty negligable. With smaller transisters, you have can afford to have less voltage do the same amount of work and have less current flow through to accomplish the same noticable logic. Less current and voltage means less heat and hence, better yield (more MHz).

 

[Platinum321]

Smaller transistor allows the chip to run cooler because of a reduced resistance. This in turn allows the chip to run harder w/o worrying about heat limitations. More importantly, with less resistance, the signals do not degraded as much in transition in between gates which allows the signal to be latched more quickly. This in turns allows the designer to increase the frequency of the clock and hence you see an enormous differences between a smaller process. Although this is the main reason for the increase clock, there are many other advantages that others have mentioned such as space, power, and $$$ saved on faulty silicon

One more thing, electricity travels light speed, but the difficulty is in getting a transition to happen fast in a device. You can't do anything unless that happens. The bigger the gate (composed of transistors), the faster the signal transitions. But big gates requre more power, add more capacitance (added delay), and take up more real estate so in designing, you need to to balance this aspect.

**made a mistake, bigger drivers = added capacitance not resistance **

Basically, when one designs for the next increase in clock frequency, you just need to balance the above combination. Ie: There are tools that will tell the designer which path is causing the most delays. With that knowledge, he/she would work on that path and most likely add bigger drivers to improve transition. To account for this increase, the paths that are very fast can be slowed down by added weaker drivers, etc. Anyhow, I don't know why I spent this time to type this but hopefully it helped someone. Of course, there may be things I've forgotten about but this is the gist.

For the northwood project (being the first .13 micron), less work was needed to manually work on individual paths. But in a project like the P3 and Athlons, which have just about reached their limit, the engineers are probably working very hard to find clever ways of optimizing paths. Like anything, the closer you get to the threshold, the more difficult it becomes. Ie: Although a good company can easily gain 70% or so marketshare, the last 10% is very difficult and probably not worth the effort unless they are desparate. My guess is that the engineers at AMD are working VERY hard to squeeze every last bit of juice out of the Athlons. It probably helps to be creative because it becomes a puzzle that just gets more difficult.

 

[CTho9305]

smaller transistors can switch faster than larger ones. Also, the speed of light does in fact matter. 186,000 miles per second = 12767040000 inches per second. at 1GHz, you can have at most 12.7 inches as your longest path. at 2GHz, 6 inches. Electricity also does not "travel" at exactly the speed of light - it varies depending on the material.

 

[Quad]

please correct me if i'm wrong, but:
by decreasing the length of the interconnect (the wire that connects 2 transistors together), the electrical resistance is also decreased, which affects many factors such as heat produced and power required. This in turn allows the engineer to raise the clockspeed because he/she is no longer faces the same limitations of heat/power as 0.18 chips.

but a few people have said that CPUs with 0.13 micron interconnects also have smaller transistors, that are able to switch faster. Is this always the case when the fab process is changed? smaller interconnects come with smaller transistors?

and is it also correct in saying that clockspeed is the rate at which the transistors switch on and off?

thx in advance

 

[Platinum321]

quad -

.13 is NOT the size of the interconnect. The interconnect is just a wire and varies depending on the requirements. To really understand what is reduced you need to understand what a transistor is made of. A transistors is made from silicon that are doped (meaning excess electrons or protons) a certain way. So there are two channels that are n- doped on two side inside p doped SI (back to back diodes). What connects the two channel is the poly (consist of multiple elements mix; i forget what) and this is where the voltage is applied to get current to flow from the left to right channels. It turns out that the amount of current that travels between the channel is correlated with the length of the poly! (reduce L ~ >current) SO, when they talk about transistor size reduction, it is this POLY length that gets reduced (there's many difficulty involved in reducing this length). Anyhow, this length is CONSTANT in a particular process (ie: .13micron = length of poly). More current means more drive which means faster transistions. Alright, so now you know that the length remains constant in a process.. but now you ask.... are all transistors equal? NO.... because another factor is the WIDTH of the poly that CAN vary within a process. Current = W/L *(other stuff)... As you can see, if you want a stronger transistor, you can increase the size of the width. But the downside is inceased capacitance which leads to added delay! Here again, it's a balancing act that engineers have to deal with.

Do you see how a transistor switches? When no voltage is applied, the transistor (for nmos) does not conduct so you get a ZERO value. When a voltage is applied, you get conduction (a ONE value). Transition refers to how fast you go from zero to one. The more current that faster the transition. The other type of transistor is the pmos which does the opposite (voltage = 0, no voltage = 1). When you combine the two, you get CMOS (complementary metal oxide silicon). With this stuff, you can make gates which does boolean logic. From there, the sky is the limit!

Regarding electricity and light speed... that's very difficult to say. Because light does not travel light speed depending on the medium (ie: light is slower in water). So what is light speed? hehe..

 

[pm]

<< 0.13 is NOT the size of the interconnect. >>

I agree insofar as there are typical 6-7 interconnection layers on a 0.13um process. But 0.13um usually does correspond to the lowest level of interconnect - the polysalicide/silicide that makes up the actually gate and wiring to the gate of the transistor. The lowest metal layer (M1) scales with process as well so that you can hook up the devices effectively. Besides, the original poster mentioned length - which is a valid point - not interconnect pitch which is what you are referring to.

What is the term "process" referring to?
The process size usually refers to the small feature that can be accurately resolved by a process. This is typically the width of the polysilicon that makes up the gate of the transistor. This defines the length of the gate of the transistor (but not the actual distance between one terminal (the drain) and the other terminal (the source) - this is known as the 'effective length' or Leff and is always lower than the measured minimum feature size (in this case, 0.13um)). This feature is the minimum feature that can be accurately resolved by the optics/laser/lithography of the process.

Benefits of reducing the process size (AKA 'process scaling')
The specifics of scaling probably fall into the highly technical catagory. I could write several paragraghs describing why things improve, but the description of the various interactions can be fairly confusing. Suffice to say that scaling improves three things: devices per unit area, dynamic power dissipation and logic and transistor switching speed. Devices per area improves by 2x, power usually dropped by about 30% and performance usually improved by about 30%.

The single biggest reason that manufacturer's scale process technology is that it doubles the number of transistors in a given area. If you reduce both the x and y dimensions of a two-dimensional object by 30%, you actually reduce the area of the object by 50%. Given the costs involved (well into the billions per fab), the benefits of scaling towards performance and power would probably not be substantial enough benefit. But the fact that you can double the number of transistors per a given area, is a huge motivation to invest in future fabrication processes.

The power reduction of scaling is steadily slowing down when comparing generation to generation. Power is made up of two parts: dynamic power (the power required to switch transistors and wires) and static power (the power that leaks through the device just by virtue of having it powered up). Reducing the feature size reduces the dynamic power due to a capacitance reduction, but the static power (AKA 'leakage') increases by an order of magnitude per each process generation. Prior to 0.25um, static power leakage was practically ignorable. At 0.18um, it started to be noticeable. At 0.13um, it is a significant problem, and 0.09um and static power are, in a word, interesting. Partially depleted SOI solves part of the leakage problem, fully depleted SOI solves another part, and a high-K gate dielectric will solve the third part. But the last two are still a ways away from implementation in the real world (outside of the labs).

The performance improvement is also losing a little steam. A process engineer can trade off performance against power, and with static power increasing a lot of the 0.13um processes have started to play this card. So if it seems like most 0.13um processes are not seeing the performance improvement of 30% that were seen in the past... they aren't.

Patrick Mahoney
Microprocessor Design Engineer
Intel Corp.