What effect do you think Intel/Micron 3DXpoint DIMMs will have on software development?

Discussion in 'Memory and Storage' started by cbn, Dec 2, 2017.

  1. cbn

    cbn Lifer

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    On the server level?

    On the client level?

    One effect, of course, will be a higher amount of memory per dollar than we are normally used to seeing in servers, but also (most likely) a higher absolute amount of memory as well.
     
    #1 cbn, Dec 2, 2017
    Last edited: Dec 2, 2017
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  3. cbn

    cbn Lifer

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    Two in memory applications I am interested in:

    Blender and R Programming language.
     
  4. cbn

    cbn Lifer

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    As a reference point here is the current on demand pricing for Amazon EC2:

    https://aws.amazon.com/ec2/pricing/on-demand/

    Scrolling down to "memory optimized" there are several options. The following is Linux with US East (Ohio) as the region:

    NOTE: These can also be had in reserved and spot instances (both of which are priced lower).

    I bring this up now because eventually I will to compare to Amazon EC2 memory optimized instances using 3DXpoint DIMMs.
     
    #3 cbn, Dec 3, 2017
    Last edited: Dec 3, 2017
  5. cbn

    cbn Lifer

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    Thinking about this more today, here is a scenario I am wondering will pan out:

    1. 3DXpoint DIMMs first appear on server. (This is the direction we know of so far).
    2. 3DXpoint (at some die size) begins to be used stacked on package with CPU chiplets for Intel Servers using EMIB. (as well as AMD Server).
    3. These same CPU chiplets (with stacked 3DXpoint on package) begin to be used as building blocks for consumer processors. (Eg, low power quad core notebook chips)
    4. 3DXpoint (low bin) begins to be used for IoT processors.
    5. 3DXpoint DIMMs begin to be used on consumer desktops.
     
    #4 cbn, Dec 4, 2017
    Last edited: Dec 5, 2017
  6. cbn

    cbn Lifer

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    Some info I got from the link in this post.

    http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=/netahtml/PTO/srchnum.html&r=1&f=G&l=50&s1="20160276022".PGNR.&OS=DN/20160276022&RS=DN/20160276022


    So a high endurance layer design has slower access time. In contrast, the low endurance layer design has faster access time.

    So how would Intel/Micron use this to their advantage? Read cache (using the low endurance layer)?
     
    #5 cbn, Dec 5, 2017
    Last edited: Dec 5, 2017