What do you think Micron's new memory is going to end up being?

[cbn]

See graph below from the following Feb 2017 Anandtech article:

https://www.anandtech.com/show/1110...ce-roadmap-updates-forecasts-and-ceo-retiring

Separate from 3D XPoint, Micron is working on at least one other new memory technology, as an in-house project instead of a collaboration with Intel. This new technology has not been named by Micron, but it will apparently allow for DRAM-like performance, which would be significantly higher than what 3D XPoint can deliver. This unspecified technology also has a clear potential for cost scaling, perhaps through increasing layering. The target it to be a bit slower and cheaper than DRAM, taking into account where DRAM technology is expected to be by the time this new memory comes to market. This is not at all an imminent revolution, and it could be a decade before it is mass produced and getting used in mainstream situations.

I was thinking maybe not 3DXpoint, but something very similar using a cross point structure and a larger cell size?

From Micron's own patent we do know they are capable of making a faster access version of 3DXpoint at the cost of reduced endurance:

http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=/netahtml/PTO/srchnum.html&r=1&f=G&l=50&s1="20160276022".PGNR.&OS=DN/20160276022&RS=DN/20160276022

Some embodiments include architectures in which two or more memory array decks are vertically stacked. One or more of the stacked decks is configured to have different operational characteristics relative to others of the stacked decks. For instance, one or more of the decks may be configured to have rapid access times suitable for utilization in XIP (execute in place) applications and/or dynamic random access memory (DRAM) emulation applications, and one or more others of the decks may be configured to have stabile, possibly slower access, storage suitable for utilization in long-term storage applications. Further, one or more of the decks may be configured to have more endurance than others of the decks. For instance, one or more of the decks may be suitable for a lifetime of approximately 100,000 cycles, whereas one or more others of the decks may be suitable for about 1,000,000 cycles (in other words, at least one of the decks may have a durability of at least about 10-fold more cycling times than another of the decks). The difference between the endurance of the decks may result from structural differences between the decks. For instance, a deck with higher endurance may have reduced thermal disturb and/or other memory-loss mechanisms as compared to a deck with less endurance. However, the deck with less endurance may have other advantages (for instance, faster access times, etc.) as compared to the deck with higher endurance. Accordingly, each memory array deck may be tailored for applicability relative to specific memory functions.

So perhaps the new memory is going to use that faster access (but low endurance) 3DXpoint design with a larger cell size to regain endurance? Then scale with increasing the number of layers.

With that noted, judging by the cost per bit in that graph above the size of the cell would have to be fairly large (almost twice as large) as 3DXpoint.