What do you think AMD will do with Zen 8C/16T dies with a Mem Controller defect?

[Doom2pro]

I like the Threadripper source, only requires quad channel, so assuming Threadripper doesn't require only 2 dies, they could take 3 to 4 defective Ryzen dies with gimped Memory Channels to create a Threadripper SKU that satisfies the quad channel memory.

 

[VirtualLarry]

Has there ever been a proposal to "extend" a PCI-E x16 physical slot, with an additional slot extension? I'm thinking, pins for "Infinity Fabric", for AMD, and "NVLink" for NVidia.

Of course, that would mean that we would have defacto "NVidia-only" and "AMD-only" video-card slots.

 

[cbn]

(snip) the packaging on the chip would get really confusing considering the different configurations and which Mem Channels would be possibly bad.

There should only be two package configurations (I would think).

A package configuration using four dies with broken memory controller on the same side as the Southbridge.

A package configuration using four dies with broken memory controller on the side opposite the Southbridge.

(See die shot in opening post)

The other question would be whether or not AMD even had enough chips with one bad mem controller to make any of this worthwhile.

Well the memory controller is quite large......so I would assume AMD would accumulate these single memory controller broken dies at the same rate they accumulate hexcores (since one controller is about the size of two Zen cores).

 

[Topweasel]

There should only be two package configurations (I would think).

A package configuration using four dies with broken memory controller on the same side as the Southbridge.

A package configuration using four dies with broken memory controller on the side opposite the Southbridge.

(See die shot in opening post)



Well the memory controller is quite large......so I would assume AMD would accumulate these single memory controller broken dies at the same rate they accumulate hexcores (since one controller is about the size of two Zen cores).

Well those and the standard packaging so that would be three complicated packages for one low volume HEDT platform. Just because something might be technically feasible doesn't mean the product itself is.

Also I have brought it up before but AMD seems content (well up until the 8c and 16c EPYC rumors yesterday) to not have any overlap on their product line. I doubt they are interested in making a more complex process of using these crippled dies, to sell them at the top of the TR stack and impede into their EPYC lineup.

As for how many are bad? Who knows but remember a bad core doesn't always mean one that doesn't work. If one can't clock above 2GHz, bin it for a 1600 or TR12. Memory controllers wouldn't need to clock up that high. Therefore much less likely to have an issue.