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What determines the jump in chip feature sizes?

It's a size that results in approximately 1/2 of the area of the previous generation (rounded in some unfathomable way that doesn't always seem to be consistent).

Thus, (130nm x 130nm) / 2 =~ (90nm x 90nm).

The sizes are chosen by ITRS.

 
Originally posted by: pm
It's a size that results in approximately 1/2 of the area of the previous generation (rounded in some unfathomable way that doesn't always seem to be consistent).

Thus, (130nm x 130nm) / 2 =~ (90nm x 90nm).

The sizes are chosen by ITRS.
Click to expand...

 
It's kind of a self fulfilling prophecy in my opinion. When people attempt to draw at a smaller process, they need some 'goal' or 'target' in mind that will be competitive with what the other company is doing. A shrink of 0.7 seems to be the most popular due to the introduction of Moore's law which emphasized the double of transistor density (or count or something on that line) every generation. Every company thinks the other company is aiming for that, so they do it to be competitive.
 
Think about how much it costs to design a process. You also have to design and build the process tools to manufactur it (well, a subset needs to be built to support the new, smaller process technology the issues that go with it such as increased particle sensitivity). Then you have to install these new tools in a factory to make parts on this new, smaller process. Basically, given how much it costs, if you DON'T at least double your die count per wafer, then you have lost money.

The 110nm process looks more like a CYA type of thing: they needed to decrease die cost (either by decreasing wafer cost or getting more die per wafer) but they didn't have the ability (financial, technical, time, other) to go all the way to the "next" step. So, they analyzed their current 130nm process and optimized a few layers (which may have entailed purchasing a few new tools, but nothing like going all the way to 90nm) to allow them to shrink the critical layers down to 110nm. More die per wafer. Better performance (generally speaking...). Low cost to implement.
 
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