What are the differences b/n P-II and P-III? PM please help

[Zenmervolt]

Other than alterations to the instruction sets, what differentiates the P-II from the P-III, architectually I mean? Please don't say that the P-III can be had in a Socket 370 form, that doesn't count. I heard that prior to the P-IV the P-Pro was the last Intel chip with a "new" trace architecture, if that is so are P-III's just fab shrinks of P-II's so they can run at higher frequencies? PM, if you're around please answer this.

 

[BreakApart]

P2 had off die cache 512k(running 1/2 processor speed), P3 has on-die cache 256k(running processor speed) and lower micron(size). Also lower voltage required for P3 over P2.

Yes there were a few new instructions also...

 

[pm]

The single biggest difference aside from the changes to the instruction set, is that the L2 cache is moved from off-chip (on the slot) to on-chip and the latency has improved. There are minor other changes (such as the move from 0.25um process technology to 0.18um) and a few minor architectural changes such as some errata fixes.

There were substantial changes to performance and the instruction set from the Pentium Pro -> Pentium II -> Pentium III, but unlying core microarchitecture remained similar throughout the three.

 

[Zenmervolt]

Much obliged PM.

Aaron Meyer

 

[BreakApart]

what am i chopped liver? Rofl....

 

[pm]

Breakapart, ROFL - well maybe not rolling, nor on the floor, but I did laugh.

 

[Zenmervolt]

Break: Sorry, I meant no offense. Just that PM works for Intel and having seen his descriptions on other posts I was looking for his opinion specifially. Please understand that I hold you at no lower a level than tuna fish. 😉 j/k From now on I'll be more careful on whom I thank. Seriously, thanks to both of you.

 

[pm]

You can always send a PM or email me, Zenmer.

 

[kombatmud]

Actually the original change from P-II to P-III (katmai) was adding Streaming SIMD Extensions (SSE), adding the processor serial number (which noone likes), and offering higher clock speeds as well as offering 133MHz bus speeds on some models (designated with a B). When they went from the katmai core to the coppermine core (designated with an E) they also shrunk the die from .25uM to .18uM and switched from 512k on-package half-speed cache to 256k on-die full speed cache (which also allowed them to offer socket 370, since they no longer needed a PCB to but the cache chips on).