Nice technical analysis ... now if only the fellows at tecchannel had the faintest idea about playing with a chipset's performance optimization registers (and the VIA chips have quite a lot of those!) .
So ... as a teacher I'd say well done, but incomplete, thus conclusions not valid.
After all, they contradict themselves by confessing that the "chipset flaw" can easily be remedied by programming it differently ...
It's a matter of fairness on the PCI bus - as a system designer, you need to decide whether you want good throughput from a single high performance card, or whether you want a good balance minimizing the risk of losing data from/to isochronous devices like sound or TV cards. To get the latter fairness, you need to limit burst lengths to give the next device a chance to win the bus and finish some of its stuff. You can't have both anymore with the level of saturation we now have on the PCI bus.
regards, Peter