VHDL help

[Deeko]

Ok, I'm trying to write a 32 bit adder, composed of 32 generated full_adders. Most of it works...except for one part. I have a signal, c32_in, which stores the carry-out from each adder, and the next adder uses it for the carry-in. It reads in in properly, but does not store the carry-out. I don't understand why...I do it the same way I output sum, and that works...

 

[Deeko]

I fixed it.

c32_in <= "000000000000000000000000000000000";

needed to be replaced with

c32_in(0) <= '0';