VHDL- Error help, using ISPLEVER 7.2

[cirthix]

@E: CL123 :"C:\my_designs\vp2290b\vp2290b\src\dvi_tcon.vhd":74:2:74:3|The logic for LINE_DONE does not match a standard flip-flop

The process in question:
LINE_TRIGGER: process(CLOCK) begin
if (DE'event and DE='0') then LINE_DONE <= '1'; else LINE_DONE <= '0'; end if;
end process;

Does this mean that the process as written is nonsynthesizable?

 

[degibson]

Try this:
LINE_TRIGGER: process(CLOCK) begin
if (DE'event and DE='1') then LINE_DONE <= '0'; else LINE_DONE <= '1'; end if;
end process;

The above matches the if-clear-else-operate model exactly... honestly, there's no good reason a synthesizer should prefer it over yours, but maybe it will. My VHDL is rusty, so I might also be missing something about sensitivity.

 

[cirthix]

Thanks degibson, but I beleive that that would also fail synthesis. The code that I came up with to fix this is:

signal vsyold: std_logic;
LINE_TRIGGER: process(CLOCK, DE) begin
deold <= DE; if (deold = '1' and DE='0') then LINE_DONE <= '1'; else LINE_DONE <= '0'; end if;
end process;