VHDL and RS232

[lambchops511]

hi guys

im new to vhdl and im doing a bit of side project work

im coding a IO Module to communicate between a FPGA and a serial port to the computer

How would i do the initial syncronization? and how would i sync my internal fpga clock to the rs232 data transfer clock

how should i do error checking and such .i saw the rs232 do the 8N1 . is that automatically implemented by windows (or hyperterminal)?

thanks

 

[tex1138]

You will need to take your FPGA's clock frequency into account... set up a timer to sample the incoming RS-232 signal several times faster than the bitrate. For a start bit, you're just looking for the first time you see the signal at '0', and you know the bit period after that. You could just keep whichever sample falls in the middle of each bit period, or do a comparison of several if you want to be extra robust.

Register the incoming signal twice in a row before using it. This will prevent metastability problems in the FPGA.

 

[Lord Banshee]

For the Clock. you will have to design a circuit that divides the clock. Can do with a counter, 74163 for example.

Then you have make some kind of state machine what would do asynchronous serial transmission, if you do not know what this is look it up on google. But basically the computer will send and receive data via the Tx/Rx lines on the serial cable, you have to find the start bit and then sample at the middle of each bit. It is asynchronous because there is no clock to fellow.

You still need a RS232 chip for your fpga signals.. The RS232 chip will make the +-12 volts (or what ever comes out of your pc) to TTL logic (ground, 5 volts).

i hope this helps get you started.

 

[gbuskirk]

You are designing a UART (Universal Asynchronous Receiver / Transmitter). This is a very old design problem and has been done many times over. Google "UART" and I'm sure you'll find something, maybe a design in VHDL even.