Verilog / VHDL / VLSI project ideas

[lesch2k]

i am looking for a verilog or vhdl program idea for an independent study course.

any ideas, any interesting projects you have worked on?

last semester i did some basic stuff like a traffic light simulator and a multiplier and some design work including a cache architecture design

 

[amoeba]

I did a Design for Testing circuit in verilog and cadence schematic. Uhm, you could try to write a pipelined architecture in verilog or vhdl, download it on to some chip and see if it runs.

 

[shuan24]

What year are you?

 

[lesch2k]

Originally posted by: shuan24
What year are you?

sr. EE major, took the only undergrad VLSI course last semester

 

[HonkeyDonk]

in my VHDL class i took, we did a stopwatch model for our final project. We had a lcd display and a pad w/ 3 buttons to simulate the switching between modes (stopwatch, regular clock, alarm) and you could program the alarm, stop/start the watch, etc. Everything like a regular watch/stopwatch could do.