Im trying to write a program for a decoder using two smaller decoders instantized in a module. I can bring in the decoders no problem but I need to invert the enable bit on one of the two decoders and I cant figure out how.
this is the 2 to 4 decoder, im trying to put two together to make a 3 to 8 decoder below.
this includes a few things ive tried and commented out. The best way ive gotten it work was just by inverting the in[2] in one by saying in[!2]. this would synthesize and run but not quite right. the help for my assignment recommends using the "not inverter0(wire1, in[2]) piece but I dont think that will work unless I can link the inverter to the enable bit by assigning wire to the enable bit of the 2-4 decoder. I cant seem to make that work though that was why I did the full module header and commented it out. I would appreciate any help.
Thank you
Code:
module mydecoder24vlog(en, in, out);
input en;
input [1:0] in;
output [3:0] out;
reg out;
always@(in or en)
begin
if(en == 1)
begin
case(in)
0: out = 4'b0001;
1: out = 4'b0010;
2: out = 4'b0100;
3: out = 4'b1000;
endcase
end
if(en == 0)
begin
out = 0;
end
end
endmodule
this is the 2 to 4 decoder, im trying to put two together to make a 3 to 8 decoder below.
Code:
/*module mydecoder24vlog (en, in, out);
input en;
input [1:0] in;
output [3:0] out;
endmodule*/
module mydecoder38vlog(in, out);
input [2:0] in;
output [7:0] out;
wire wire1;
mydecoder24vlog decoder1 (in[2], in[1:0], out[7:4]);
mydecoder24vlog decoder0 (in[2], in[1:0], out[3:0]);
// assign wire1= decoder0 en;
//not inverter0(wire1, in[2]);
endmodule
Thank you