Verilog assign statement help

[soydios]

A little Verilog question that has been driving me up the wall: why does the following code produce undefined values in the assign statement and correct values in the display statement?

assign cache_uid = (transmit_uid & {uidw{transmit}}) | (receive_write_uid & {uidw{receive}}) | (outstanding_write_uid & {uidw{outstanding}}); $display("cache_uid=%h, try again=%h", cache_uid, (transmit_uid & {uidw{transmit}}) | (receive_write_uid & {uidw{receive}}) | (outstanding_write_uid & {uidw{outstanding}}));

And printed in the console display:
cache_uid=XX, try again=88

 

[Cogman]

$display just spits out what is currently on the line. Your implementer (or whatever its called) is recognizing that some of the variables you are using for cache_uid are capable of being transient during the assign.

At the time that $display is being called, the values aren't unknown. That isn't always true.

I'm not an extreme verilog expert, so take my advice with a grain of salt 😉

 

[degibson]

Verilog assigns aren't evaluated until a signal changes. They are more or less equivalent to:

always@(*) begin
  cache_uid <= signal & signal2 | signal3 ...
end

... But the behavior of $display is dependant in the interpreter, as Cogman pointed out. Try an initial block that sets the input signals to known states, assuming they are regs. If not, write a testbench module and assign them to known states.