- Nov 23, 2001
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https://www.anandtech.com/show/11717/the-amd-radeon-rx-vega-64-and-56-review/2
In this article they state the following:
"On all iterations of GCN, AMD has bundled CUs together in a shader array, with up to 4 CUs sharing a single L1 instruction cache and a constant cache. For Vega 10, that granularity has gone up a bit, and now only 3 CUs share any one of these cache sets. As a result there are now 6 CU arrays per compute engine, up from 4 on Fiji."
Is this an error ? has it really changed to 3 CUs sharing an L1 block or was that just miscommunication with the amd contact ?
it should still be 4 CUs sharing an L1 "cache set", this would mean 4 L1 cache sets per compute engine and 16 CUs per compute engine. I don't see how 3 would work ... 6 "CU arrays" don't make sense because there are 16 CUs not 18 or 12 ...
Am I right here ?
In this article they state the following:
"On all iterations of GCN, AMD has bundled CUs together in a shader array, with up to 4 CUs sharing a single L1 instruction cache and a constant cache. For Vega 10, that granularity has gone up a bit, and now only 3 CUs share any one of these cache sets. As a result there are now 6 CU arrays per compute engine, up from 4 on Fiji."
Is this an error ? has it really changed to 3 CUs sharing an L1 block or was that just miscommunication with the amd contact ?
it should still be 4 CUs sharing an L1 "cache set", this would mean 4 L1 cache sets per compute engine and 16 CUs per compute engine. I don't see how 3 would work ... 6 "CU arrays" don't make sense because there are 16 CUs not 18 or 12 ...
Am I right here ?
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