Various: AMD / HBM Analysis

[BFG10K]

Timely considering this a very hot topic right now:

http://www.anandtech.com/show/9266/amd-hbm-deep-dive

http://techreport.com/review/28294/amd-high-bandwidth-memory-explained

http://www.tomshardware.com/news/amd-high-bandwidth-memory,29116.html

http://hothardware.com/news/amd-details-high-bandwidth-memory-hbm-interface-technology

http://www.extremetech.com/extreme/...d-unveils-its-plans-for-high-bandwidth-memory

 

[Silverforce11]

"At the same time this also calls into question memory capacity – 4 1GB stacks is only 4GB of VRAM – though AMD seems to be saving that matter for the final product introduction later this quarter."

4GB models first, 8GB models (dual-link interposer) later..

Very lame, I was hoping for 8GB out of the door asap, skipping 4GB upgrade option altogether.

 

[ShintaiDK]

"At the same time this also calls into question memory capacity – 4 1GB stacks is only 4GB of VRAM – though AMD seems to be saving that matter for the final product introduction later this quarter."

4GB models first, 8GB models (dual-link interposer) later..

Very lame, I was hoping for 8GB out of the door asap, skipping 4GB upgrade option altogether.

2GB HBM stacks are needed, no made up "dual link interposer".

 

[ShintaiDK]

Anandtech also includes estimated power consumption numbers.

14.6W for 4GB HBM(theoretical product), 31.5W for 12GB GDDR5(Titan X), 30W for 4GB GDDR5 (290X).

 

[itsmydamnation]

the question is does that include memory controller, or just Dram and bus.

I don't see 4gb as being an issue anandtech madness ( hint look at oculus recommendations)........

 

[twjr]

Anandtech also state that HBM allows for 2-8 stacks to be used each carrying 1GB of memory.

 

[Rvenger]

If this is the case then I am waiting for 16nm. Not even going to bother if 4gb, honestly.

 

[sandorski]

"At the same time this also calls into question memory capacity – 4 1GB stacks is only 4GB of VRAM – though AMD seems to be saving that matter for the final product introduction later this quarter."

4GB models first, 8GB models (dual-link interposer) later..

Very lame, I was hoping for 8GB out of the door asap, skipping 4GB upgrade option altogether.

Where does it say that? The way I read it seemed to leave it open that 8gb could be available Day 1, AMD was just not going to mention it at this time.

 

[Silverforce11]

Where does it say that? The way I read it seemed to leave it open that 8gb could be available Day 1, AMD was just not going to mention it at this time.

I hope so man.

I would spend a lot on a nice flagship if I was more assured it was still capable 2 years down the road.

Case in point, 680/770 2GB can't even enable Ultra textures in a few games, while 7970 can and manage it at playable (45-50) fps without MSAA.

To me, Texture Quality >> most other graphics options and that is most dependent on vram quantity.

 

[The Alias]

idk I'm confident in AMD's ability to optimize their memory usage like Macri said they did.

 

[Flapdrol1337]

4GB is fine, in games that use dynamic texture streaming it'll give perfect quality, games that don't aren't the best looking anyway.

 

[Termie]

TechReport clearly states that 4GB is the limit this generation.

This first-gen HBM stack will impose at least one limitation of note: its total capacity will only be 4GB. At first blush, that sounds like a limited capacity for a high-end video card. After all, the Titan X packs a ridiculous 12GB, and the prior-gen R9 290X has the same 4GB amount. Now that GPU makers are selling high-end cards on the strength of their performance at 4K resolutions, one might expect more capacity from a brand-new flagship graphics card.

Source: http://techreport.com/review/28294/amd-high-bandwidth-memory-explained/2

 

[realibrad]

I find it weird that so many are already sing 4GB wont be enough. Wait until the reviews come out. If the card can do what you want, great, if not, skip it. Why would anyone want to skip a card because of a spec that may or may not be a limit?

 

[sm625]

Since these gpu footprints will be so small, they might put two on a pcb just to be able to claim 8GB. I guess they could probably fit up to 4 on a pcb, along with a big water block. There's your 16GB 1000W behemoth.

 

[Skurge]

TechReport clearly states that 4GB is the limit this generation.



Source: http://techreport.com/review/28294/amd-high-bandwidth-memory-explained/2

Anandtech state that they have the option of using 8 stacks of 1GB each. No dual-link anything needed.

 

[Azix]

Is this an official image? If so, on one side we see at least three chips. 2 at top middle and bottom middle with three on the other side is 8. Unless its asymmetrical. It should be 6 GB minimum if that is a real image.

assuming its three because one of the chips looks like its in the middle relative to the GPU. And assuming an actual picture is better representation than an illustration.

Also, if the rumors are true and it has over 512GB/s that is assumed for 4 stacks, then it has more than 4 stacks.

Therefore, as a result of, due to and based on this wild speculation I hereby declare that fiji has SIX GB OF VRAM!!!!

Anandtech state that they have the option of using 8 stacks of 1GB each. No dual-link anything needed.

or Six. But yeah, just use more stacks. Heat is the main problem

 

[ShintaiDK]

Anandtech state that they have the option of using 8 stacks of 1GB each. No dual-link anything needed.

That would require a 8192bit memory controller.

 

[Azix]

That would require a 8192bit memory controller.

Not familiar with how memory works, but just because it can interface with that kind of controller, does it mean you have to have one for it to work?

GDDR5 works with a good variety of memory controllers from crappy-bit to 512bit. The magical interposer could address that as well.

 

[sakete]

I was wondering the same thing. On one of the diagrams you see multiple stacks. So while one stack might be limited to 4x 1GB HBM, who says that PCB is limited to only 1 stack of HBM?

 

[Cloudfire777]

Anandtech also includes estimated power consumption numbers.

14.6W for 4GB HBM(theoretical product), 31.5W for 12GB GDDR5(Titan X), 30W for 4GB GDDR5 (290X).

Exactly. I earlier said HBM wont gain as much power wise against GDDR5.
Although AMDs own marketing slides and other members here said 50W+ gains.

Marketing and fact spinning, thats what it is

 

[ShintaiDK]

I was wondering the same thing. On one of the diagrams you see multiple stacks. So while one stack might be limited to 4x 1GB HBM, who says that PCB is limited to only 1 stack of HBM?

There is no limits as such to the stack amount besides the memory controller and PCB size. But each stack needs its own 1024bit interface for HBM.

Xeon Phi for example uses 8 stacks of HMC. But unlike HBM, HMC uses a serial interface with much less pins.

 

[TemjinGold]

I would totally do 6 and not even look at 4. All the people who keep saying no big deal with 4 if it runs everything today are still missing the point. I don't want my expensive high end gpu to only run games fine TODAY.

 

[Erenhardt]

That would require a 8192bit memory controller.

Yeah, and r9 290X 8GB has 1024Bit memory controller, right? C'mon. Stop the FUD.

 

[Silverforce11]

Exactly. I earlier said HBM wont gain as much power wise against GDDR5.
Although AMDs own marketing slides and other members here said 50W+ gains.

Marketing and fact spinning, thats what it is

That's the ram chips only. TR mentions it specifically. AMD has not divulge potential power savings on the actual memory controller & interconnects (memory subsystem).

 

[Headfoot]

I'm certain there is a way to interleave 2 1GB stacks into a single 1024-bit channel, memory has always by its very nature been interleaved. This "dual link interposer" business is totally made up as far as I can tell... unless y'all are trying to talk about merely interleaved memory on the same bus.

The Anandtech write up even explicitly called out that it should be easier to incorporate control logic now that its all on an interposer. GPU would see a 2GB memory pool on that 1024-bit bus, control chip could split it across the two attached stacks (much like PLX bridges for PCIe for example). It's for sure possible.

Now whether AMD actually did this or not is an entirely different issue. The slide seem to imply they designed for 4 GB. It could be that an interleaved design ruins the latency advantage of HBM or any other variety of issues they identified with such a solution. I trust that there would be a reason, even if its just that going to 8 with an interleaved design adds too much cost.