The classical UV erasable EPROM uses the FA-MOS transistor model, with a floating gate inside the oxide layer. Has anyone heard of this same structure made with the use of the new dielectric materials such as silicon nitride, or silicon carbide?
Originally posted by: yellowfiero
The classical UV erasable EPROM uses the FA-MOS transistor model, with a floating gate inside the oxide layer. Has anyone heard of this same structure made with the use of the new dielectric materials such as silicon nitride, or silicon carbide?
You have a BSEE from GMI, an MSEE from Cornell, and you are Faculty in a school of EECE -- and you are asking us dolts about some crazy floating gate inside an oxide layer?? :Q
I'm a semiconductor test engineer and I don't have the slightest clue what you are talking about. ROTFL.
I've seen ONO stacks used but not entirely silicon nitride or SiC. I'm sure there has been research done on the subject, perhaps a search of IEEE abstracts would give you more results on the subject.
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