- May 18, 2001
- 24,117
- 2
- 0
UPDATE: Now the same hack is stating that Prescott will be 64bit
See HERE.
Read this Cr@p
So more pins = more 'bit-ness', fvck off, fool.
So I emailed this:
Then tonight I get this reply from him:
LOL! Not enough address pins to do 64bit memory addressing? LMFAO!
So I sent this by return:
I'll keep you all updated. Made me laugh my t!ts off.
New reply
Super Tool rides again, so I reply:


Read this Cr@p
So more pins = more 'bit-ness', fvck off, fool.
So I emailed this:
> > Hi Charlie,
>
> I wonder, what exactly leads you to believe that you need 'more pins'
> to go 64bit operation?
>
> What part of having 64bit registers leads to extra pinouts?
>
> How many pins would I need to develop a 128bit CPU? 200 extra?
>
> I think you'll find they were laughing at you, not with you.
>
> TD.
Then tonight I get this reply from him:
Umm, how about the fact that socket 478 does not have enough address
pins to do 64 bit memory addressing. No, that couldn't be it. How about
the fact that all Intel chips with SSE2 can already do 128 bit SIMD
calculations. Basically, you don't have a clue, I would recommend that
you know what you are talking about before you criticize others, it
makes you look a whole lot less stupid.
-Charlie
LOL! Not enough address pins to do 64bit memory addressing? LMFAO!
So I sent this by return:
You really are on shaky ground suggesting you have superior knowledge fella.
And here's why:
The P4 has 8 128bit registers for SIMD calculations ONLY. These are internal registers and have a very specific application. The P4 cannot work in a fully 128bit mode. As if I should have to tell you that...
DDR Memory has always worked on a 64bit data path, so why oh why, if we are working to your standards in the shabby article, do the Athlon and P4 not have a BOATLOAD OF EXTRA PINS? Could it be that you're totally clueless to the justification of extra pins in a CPU socket solution?
If we were to use your method, the P4 is short of about 400 pins, is it not?!
Did you know that the Pentium Pro(The first P6 core) was to have 64bit extensions to x86? How many extra pins do you think that would have had? Come tell, I'd love to have your calculations.
I stand by my first assertion, that they were yanking your extremely daft chain good and hard, getting a giggle out of it at the same time.
Those who can, work in the industry. Those who can't write crap like your article.
I'll keep you all updated. Made me laugh my t!ts off.
New reply
>I'm amazed you can spell the word stupid.
>
>
Actually, the spell checker caught it.
>Do you know anything about hypertransport? What do you think is the
>difference between the A64 and A64FX, which has 754 pins vs. 939/940?
>
>
Just about everything HT wise. Talked to many of the engineers at
length. The difference between the memory A64 and the FX is the die it
was based on. FX=Opteron die, dual mem controllers etc, same chip.
Without quoting my article, know what the 939/940 difference is?
>Is it because the A64FX is 128Bit? 256Bit? Or because you know nothing
>about why the pins are there in the first place?
>
>
64, with a single 128 bit wide memory channel.
>You really are on shaky ground suggesting you have superior knowledge fella.
>
>
Not really.
>And here's why:
>
>The P4 has 8 128bit registers for SIMD calculations ONLY. These are
>internal registers and have a very specific application. The P4 cannot work
>in a fully 128bit mode. As if I should have to tell you that...
>
>
Yes. Your point?
>DDR Memory has always worked on a 64bit data path, so why oh why, if we are
>working to your standards in the shabby article, do the Athlon and P4 not
>have a BOATLOAD OF EXTRA PINS? Could it be that you're totally clueless to
>the justification of extra pins in a CPU socket solution?
>
>
No, I am right.
>If we were to use your method, the P4 is short of about 400 pins, is it
>not?!
>
>
297 pins short, rectified around next June.
>Did you know that the Pentium Pro(The first P6 core) was to have 64bit
>extensions to x86? How many extra pins do you think that would have had?
>Come tell, I'd love to have your calculations.
>
>
2 per bit, or 64 more, plus a few for overhead.
>I stand by my first assertion, that they were yanking your extremely daft
>chain good and hard, getting a giggle out of it at the same time.
>
>
OK, believe what you will.
>Those who can, work in the industry. Those who can't write crap like your
>article.
>
>
Guess I am sh!t then.
>Put this unedited into flame of the week, if you've got the stomach for it.
>
>
Actually, I don't do that column, but I'll pass it to Mike ASAP.
-Charlie
Super Tool rides again, so I reply:
Er, 940 ECC, 939 non, AFAIK.
Simply stating 'I am right' doesn't cut much mustard. You clearly stated in your "Article" that more pins = more bits. This is cr@p.
x86-64 is an extension of the x86 instruction set that adds support for 64-bit code and for system memory amounts beyond the 4GB ceiling of all 32-bit processors - the Opteron has 40-bit (1 terabyte) physical and 48-bit (256 teraybtes) virtual memory-addressing capability.
So what of the MAXIMUM 40bit memory addressing capability of Opteron? Gee, that should surely save some pins?
Seriously.