10 core EP? Oh hell yeah. That thing is going to fly in a dual socket machine.
I will be getting an Ivy Bridge E.
right saying @NTMBK.
and this is also right "Just insult each other all you want until one of your keyboards explode. Last keyboard functioning will surely show who's the biggest, baddest internet tough guy. Or not
hopefully this means native 10 core and native 6 core and we get an 8-10 core i7 for the same $600-1000 price range of the current 6 core SB-Es and hopefully even see 6 core options in the $300-500 range
hopefully this means native 10 core and native 6 core and we get an 8-10 core i7 for the same $600-1000 price range of the current 6 core SB-Es and hopefully even see 6 core options in the $300-500 range
I just cant help but imagine that such a 10 core beast would benefit massively from TX memory as in upcoming haswell .. until reviews hit the street we wont know, but just how much faster a 8 core lower clocked IB will be than a higher clocked 4 core haswell ? I'm not so sure it will run circles around it even in highly threaded apps.
A 10C IB-E i7 would most likely be too slow clocked for users to accept. Expect 6 and 8 cores.
A 10C IB-E i7 would most likely be too slow clocked for users to accept. Expect 6 and 8 cores.
It depends a lot on the instruction mix. In Linx for example, a quadcore Haswell will beat a similar clocked octocore IB. For anything at or below 4 threads Haswell will (always) win.
The lack of additional cores for Haswell is a bit disappointing, despite being known for a long time. We have had quad cores as the top mainstream since the C2Q, 6 years ago. Back then Intel was telling us we would be running thousands of cores and here we are 3 process jumps later and it hasn't happened. 6 cores would have been nice, there are plenty of applications that benefit from that already.
No one is going to write software that requires 10-20-100's of cores until it looks like the hardware will be there. The software follows the hardware everytime.
Amdahl's law along with few problems being inherently parallel enough to warrant MOAR CORES. It's mostly wasted silicon (and power that can be used for faster, fewer cores) except for edge cases (and that's even if we pretend programmers are up to snuff to extract all the theoretical performance out of every problem: something far from true)
